intel/compiler: Store Primitive ID in TCS thread payload struct

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>

src/intel/compiler/brw_fs.h

@@ -97,6 +97,7 @@ struct tcs_thread_payload : public thread_payload {
    tcs_thread_payload(const fs_visitor &v);
 
    fs_reg patch_urb_output;
+   fs_reg primitive_id;
 };
 
 struct fs_thread_payload : public thread_payload {

src/intel/compiler/brw_fs_nir.cpp

@@ -2810,17 +2810,13 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
    struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data);
    struct brw_vue_prog_data *vue_prog_data = &tcs_prog_data->base;
 
-   bool multi_patch =
-      vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH;
-
    fs_reg dst;
    if (nir_intrinsic_infos[instr->intrinsic].has_dest)
       dst = get_nir_dest(instr->dest);
 
    switch (instr->intrinsic) {
    case nir_intrinsic_load_primitive_id:
-      bld.MOV(dst, fs_reg(multi_patch ? brw_vec8_grf(2, 0)
+      bld.MOV(dst, tcs_payload().primitive_id);
-                                      : brw_vec1_grf(0, 1)));
       break;
    case nir_intrinsic_load_invocation_id:
       bld.MOV(retype(dst, invocation_id.type), invocation_id);
@@ -2847,9 +2843,12 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
       unsigned imm_offset = nir_intrinsic_base(instr);
       fs_inst *inst;
 
-      fs_reg icp_handle =
+      const bool multi_patch =
-         multi_patch ? get_tcs_multi_patch_icp_handle(bld, instr)
+         vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH;
-                     : get_tcs_single_patch_icp_handle(bld, instr);
+
+      fs_reg icp_handle = multi_patch ?
+         get_tcs_multi_patch_icp_handle(bld, instr) :
+         get_tcs_single_patch_icp_handle(bld, instr);
 
       /* We can only read two double components with each URB read, so
        * we send two read messages in that case, each one loading up to

src/intel/compiler/brw_fs_thread_payload.cpp

@@ -33,6 +33,7 @@ tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)
 
    if (vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH) {
       patch_urb_output = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD);
+      primitive_id = brw_vec1_grf(0, 1);
 
       /* r1-r4 contain the ICP handles. */
       num_regs = 5;
@@ -42,6 +43,9 @@ tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)
 
       patch_urb_output = retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD);
 
+      if (tcs_prog_data->include_primitive_id)
+         primitive_id = brw_vec8_grf(2, 0);
+
       /* r1 contains output handles, r2 may contain primitive ID, then the
        * ICP handles occupy the next 1-32 registers.
        */