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radeonsi: rename esgs_itemsize -> esgs_vertex_stride

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Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
This commit is contained in:
Marek Olšák
2023-02-20 00:26:15 -05:00
committed by Marge Bot
parent 32b8d0c19d
commit 26208698ae
5 changed files with 15 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
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@@ -140,7 +140,7 @@ retry_select_mode:
max_out_verts_per_gsprim = gs_sel->info.base.gs.vertices_out;
}
esvert_lds_size = es_sel->info.esgs_itemsize / 4;
esvert_lds_size = es_sel->info.esgs_vertex_stride / 4;
gsprim_lds_size = (gs_sel->info.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
if (gsprim_lds_size > target_lds_size && !force_multi_cycling) {

6
src/gallium/drivers/radeonsi/si_shader.c
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@@ -1066,7 +1066,7 @@ void si_shader_dump_stats_for_shader_db(struct si_screen *screen, struct si_shad
if (shader->gs_copy_shader)
num_outputs = shader->gs_copy_shader->info.nr_param_exports;
else if (shader->key.ge.as_es)
num_outputs = shader->selector->info.esgs_itemsize / 16;
num_outputs = shader->selector->info.esgs_vertex_stride / 16;
else if (shader->key.ge.as_ls)
num_outputs = shader->selector->info.lshs_vertex_stride / 16;
else if (shader->selector->stage == MESA_SHADER_VERTEX ||
@@ -1562,7 +1562,7 @@ static bool si_lower_io_to_mem(struct si_shader *shader, nir_shader *nir,
return true;
} else if (key->ge.as_es) {
NIR_PASS_V(nir, ac_nir_lower_es_outputs_to_mem, si_map_io_driver_location,
sel->screen->info.gfx_level, sel->info.esgs_itemsize);
sel->screen->info.gfx_level, sel->info.esgs_vertex_stride);
return true;
}
} else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
@@ -1585,7 +1585,7 @@ static bool si_lower_io_to_mem(struct si_shader *shader, nir_shader *nir,
if (key->ge.as_es) {
NIR_PASS_V(nir, ac_nir_lower_es_outputs_to_mem, si_map_io_driver_location,
sel->screen->info.gfx_level, sel->info.esgs_itemsize);
sel->screen->info.gfx_level, sel->info.esgs_vertex_stride);
}
return true;

2
src/gallium/drivers/radeonsi/si_shader.h
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@@ -405,7 +405,7 @@ struct si_shader_info {
ubyte culldist_mask;
uint16_t lshs_vertex_stride;
uint16_t esgs_itemsize; /* vertex stride */
uint16_t esgs_vertex_stride;
uint16_t gsvs_vertex_size;
ubyte gs_input_verts_per_prim;
unsigned max_gsvs_emit_size;

8
src/gallium/drivers/radeonsi/si_shader_info.c
View File

@@ -778,8 +778,8 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir,
if (nir->info.stage == MESA_SHADER_VERTEX ||
nir->info.stage == MESA_SHADER_TESS_CTRL ||
nir->info.stage == MESA_SHADER_TESS_EVAL) {
info->esgs_itemsize = util_last_bit64(info->outputs_written) * 16;
info->lshs_vertex_stride = info->esgs_itemsize;
info->esgs_vertex_stride = util_last_bit64(info->outputs_written) * 16;
info->lshs_vertex_stride = info->esgs_vertex_stride;
/* Add 1 dword to reduce LDS bank conflicts, so that each vertex
* will start on a different bank. (except for the maximum 32*16).
@@ -790,9 +790,9 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir,
* conflicts, i.e. each vertex will start on a different bank.
*/
if (sscreen->info.gfx_level >= GFX9)
info->esgs_itemsize += 4;
info->esgs_vertex_stride += 4;
assert(((info->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
assert(((info->esgs_vertex_stride / 4) & C_028AAC_ITEMSIZE) == 0);
info->tcs_vgpr_only_inputs = ~info->base.tess.tcs_cross_invocation_inputs_read &
~info->base.inputs_read_indirectly &

12
src/gallium/drivers/radeonsi/si_state_shaders.cpp
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@@ -771,7 +771,7 @@ static void si_emit_shader_es(struct si_context *sctx)
radeon_begin(&sctx->gfx_cs);
radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
shader->selector->info.esgs_itemsize / 4);
shader->selector->info.esgs_vertex_stride / 4);
if (shader->selector->stage == MESA_SHADER_TESS_EVAL)
radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
@@ -843,7 +843,7 @@ void gfx9_get_gs_info(struct si_shader_selector *es, struct si_shader_selector *
/* We can't allow using the whole LDS, because GS waves compete with
* other shader stages for LDS space. */
const unsigned max_lds_size = 8 * 1024;
const unsigned esgs_itemsize = es->info.esgs_itemsize / 4;
const unsigned esgs_itemsize = es->info.esgs_vertex_stride / 4;
unsigned esgs_lds_size;
/* All these are per subgroup: */
@@ -1136,7 +1136,7 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
shader->gs.vgt_gs_max_prims_per_subgroup =
S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
shader->gs.vgt_esgs_ring_itemsize = shader->key.ge.part.gs.es->info.esgs_itemsize / 4;
shader->gs.vgt_esgs_ring_itemsize = shader->key.ge.part.gs.es->info.esgs_vertex_stride / 4;
if (es_stage == MESA_SHADER_TESS_EVAL)
si_set_tesseval_regs(sscreen, shader->key.ge.part.gs.es, shader);
@@ -1472,7 +1472,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
gs_sel->info.writes_primid);
if (gs_stage == MESA_SHADER_GEOMETRY) {
shader->ngg.vgt_esgs_ring_itemsize = es_sel->info.esgs_itemsize / 4;
shader->ngg.vgt_esgs_ring_itemsize = es_sel->info.esgs_vertex_stride / 4;
shader->ngg.vgt_gs_max_vert_out = gs_sel->info.base.gs.vertices_out;
} else {
shader->ngg.vgt_esgs_ring_itemsize = 1;
@@ -3825,11 +3825,11 @@ bool si_update_gs_ring_buffers(struct si_context *sctx)
unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
/* Calculate the minimum size. */
unsigned min_esgs_ring_size = align(es->info.esgs_itemsize * gs_vertex_reuse * wave_size, alignment);
unsigned min_esgs_ring_size = align(es->info.esgs_vertex_stride * gs_vertex_reuse * wave_size, alignment);
/* These are recommended sizes, not minimum sizes. */
unsigned esgs_ring_size =
max_gs_waves * 2 * wave_size * es->info.esgs_itemsize * gs->info.gs_input_verts_per_prim;
max_gs_waves * 2 * wave_size * es->info.esgs_vertex_stride * gs->info.gs_input_verts_per_prim;
unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size * gs->info.max_gsvs_emit_size;
min_esgs_ring_size = align(min_esgs_ring_size, alignment);