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intel/compiler: Don't create 64-bit src1 immediates in opt_peephole_sel

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64-bit immediates are only allowed as src0.  Long ago, we decided to
avoid constructing such illegal situations in the IR, rather than
allowing them in the IR but then promoting bogus immediates to GRFs
later.  So, we need to fix opt_peephole_sel to not put 64-bit immediates
as src1 of the new SEL instruction.

Fixes: a4b36cd3dd ("intel/fs: Coalesce when the src live range is contained in the dst")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2816
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4692>
This commit is contained in:
Kenneth Graunke
2020-04-22 08:42:17 -07:00
committed by Marge Bot
parent 4459a70a6e
commit 259cae4442
1 changed files with 8 additions and 2 deletions
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10
src/intel/compiler/brw_fs_sel_peephole.cpp
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@@ -202,9 +202,15 @@ fs_visitor::opt_peephole_sel()
ibld.MOV(src0, then_mov[i]->src[0]);
}
/* 64-bit immediates can't be placed in src1. */
fs_reg src1(else_mov[i]->src[0]);
if (src1.file == IMM && type_sz(src1.type) == 8) {
src1 = ibld.vgrf(else_mov[i]->src[0].type);
ibld.MOV(src1, else_mov[i]->src[0]);
}
set_predicate_inv(if_inst->predicate, if_inst->predicate_inverse,
ibld.SEL(then_mov[i]->dst, src0,
else_mov[i]->src[0]));
ibld.SEL(then_mov[i]->dst, src0, src1));
}
then_mov[i]->remove(then_block);