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amd/vpelib: Restructure CDC FE/BE

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[Why]
CDC has two separate functionalities : backend and frontend.
split them into two for better resource management.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Jude Shih <shenshih@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31605>
This commit is contained in:
Jude Shih
2024-08-12 17:25:31 +08:00
committed by Marge Bot
parent 0d7f51724b
commit 259b44d97b
18 changed files with 426 additions and 252 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/amd/vpelib/inc/vpe_types.h
View File

@@ -214,6 +214,7 @@ struct vpe_caps {
int num_dpp;
int num_opp;
int num_mpc_3dlut;
int num_cdc_be;
int num_queue; /**< num of hw queue */
} resource_caps;

6
src/amd/vpelib/meson.build
View File

@@ -101,7 +101,8 @@ vpe_files = files(
'src/chip/vpe10/inc/asic/bringup_vpe_6_1_0_sh_mask.h',
'src/chip/vpe10/inc/asic/vpe_1_0_offset.h',
'src/chip/vpe10/inc/vpe10_resource.h',
'src/chip/vpe10/inc/vpe10_cdc.h',
'src/chip/vpe10/inc/vpe10_cdc_fe.h',
'src/chip/vpe10/inc/vpe10_cdc_be.h',
'src/chip/vpe10/inc/vpe10_dpp.h',
'src/chip/vpe10/vpe10_plane_desc_writer.c',
'src/chip/vpe10/vpe10_vpe_desc_writer.c',
@@ -114,7 +115,8 @@ vpe_files = files(
'src/chip/vpe10/vpe10_dpp_cm.c',
'src/chip/vpe10/vpe10_opp.c',
'src/chip/vpe10/vpe10_background.c',
'src/chip/vpe10/vpe10_cdc.c',
'src/chip/vpe10/vpe10_cdc_fe.c',
'src/chip/vpe10/vpe10_cdc_be.c',
'src/chip/vpe10/vpe10_vpec.c',
'src/chip/vpe10/vpe10_config_writer.c',
'src/chip/vpe11/inc/vpe11_command.h',

97
src/amd/vpelib/src/chip/vpe10/inc/vpe10_cdc_be.h Normal file
View File

@@ -0,0 +1,97 @@
/* Copyright 2024 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#pragma once
#include "cdc.h"
#include "reg_helper.h"
#ifdef __cplusplus
extern "C" {
#endif
#define VPE10_CDC_VUPDATE_OFFSET_DEFAULT (21)
#define VPE10_CDC_VUPDATE_WIDTH_DEFAULT (60)
#define VPE10_CDC_VREADY_OFFSET_DEFAULT (150)
/* macros for filing variable or field list
SRI, SFRB should be defined in the resource file */
#define CDC_BE_REG_LIST_VPE10(id) \
SRIDFVL(VPCDC_BE0_P2B_CONFIG, CDC, id), SRIDFVL(VPCDC_BE0_GLOBAL_SYNC_CONFIG, CDC, id)
#define CDC_BE_FIELD_LIST_VPE10(post_fix) \
SFRB(VPCDC_BE0_P2B_XBAR_SEL0, VPCDC_BE0_P2B_CONFIG, post_fix), \
SFRB(VPCDC_BE0_P2B_XBAR_SEL1, VPCDC_BE0_P2B_CONFIG, post_fix), \
SFRB(VPCDC_BE0_P2B_XBAR_SEL2, VPCDC_BE0_P2B_CONFIG, post_fix), \
SFRB(VPCDC_BE0_P2B_XBAR_SEL3, VPCDC_BE0_P2B_CONFIG, post_fix), \
SFRB(VPCDC_BE0_P2B_FORMAT_SEL, VPCDC_BE0_P2B_CONFIG, post_fix), \
SFRB(BE0_VUPDATE_OFFSET, VPCDC_BE0_GLOBAL_SYNC_CONFIG, post_fix), \
SFRB(BE0_VUPDATE_WIDTH, VPCDC_BE0_GLOBAL_SYNC_CONFIG, post_fix), \
SFRB(BE0_VREADY_OFFSET, VPCDC_BE0_GLOBAL_SYNC_CONFIG, post_fix)
/* define all structure register variables below */
#define CDC_BE_REG_VARIABLE_LIST_VPE10 \
reg_id_val VPCDC_BE0_P2B_CONFIG; \
reg_id_val VPCDC_BE0_GLOBAL_SYNC_CONFIG;
#define CDC_BE_FIELD_VARIABLE_LIST_VPE10(type) \
type VPCDC_BE0_P2B_XBAR_SEL0; \
type VPCDC_BE0_P2B_XBAR_SEL1; \
type VPCDC_BE0_P2B_XBAR_SEL2; \
type VPCDC_BE0_P2B_XBAR_SEL3; \
type VPCDC_BE0_P2B_FORMAT_SEL; \
type BE0_VUPDATE_OFFSET; \
type BE0_VUPDATE_WIDTH; \
type BE0_VREADY_OFFSET;
struct vpe10_cdc_be_registers {
CDC_BE_REG_VARIABLE_LIST_VPE10
};
struct vpe10_cdc_be_shift {
CDC_BE_FIELD_VARIABLE_LIST_VPE10(uint8_t)
};
struct vpe10_cdc_be_mask {
CDC_BE_FIELD_VARIABLE_LIST_VPE10(uint32_t)
};
struct vpe10_cdc_be {
struct cdc_be base; // base class, must be the first field
struct vpe10_cdc_be_registers *regs;
const struct vpe10_cdc_be_shift *shift;
const struct vpe10_cdc_be_mask *mask;
};
void vpe10_construct_cdc_be(struct vpe_priv *vpe_priv, struct cdc_be *cdc_be);
bool vpe10_cdc_check_output_format(struct cdc_be *cdc_be, enum vpe_surface_pixel_format format);
void vpe10_cdc_program_global_sync(
struct cdc_be *cdc_be, uint32_t vupdate_offset, uint32_t vupdate_width, uint32_t vready_offset);
void vpe10_cdc_program_p2b_config(struct cdc_be *cdc_be, enum vpe_surface_pixel_format format,
enum vpe_swizzle_mode_values swizzle, const struct vpe_rect *viewport);
#ifdef __cplusplus
}
#endif

69
src/amd/vpelib/src/chip/vpe10/inc/vpe10_cdc.h → src/amd/vpelib/src/chip/vpe10/inc/vpe10_cdc_fe.h
View File

@@ -1,4 +1,4 @@
/* Copyright 2022 Advanced Micro Devices, Inc.
/* Copyright 2024 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -36,19 +36,18 @@ extern "C" {
/* macros for filing variable or field list
SRI, SFRB should be defined in the resource file */
#define CDC_REG_LIST_VPE10(id) \
#define CDC_FE_REG_LIST_VPE10(id) \
SRIDFVL(VPEP_MGCG_CNTL, CDC, id), SRIDFVL(VPCDC_SOFT_RESET, CDC, id), \
SRIDFVL(VPCDC_FE0_SURFACE_CONFIG, CDC, id), SRIDFVL(VPCDC_FE0_CROSSBAR_CONFIG, CDC, id), \
SRIDFVL(VPCDC_FE0_VIEWPORT_START_CONFIG, CDC, id), \
SRIDFVL(VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG, CDC, id), \
SRIDFVL(VPCDC_FE0_VIEWPORT_START_C_CONFIG, CDC, id), \
SRIDFVL(VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG, CDC, id), \
SRIDFVL(VPCDC_BE0_P2B_CONFIG, CDC, id), SRIDFVL(VPCDC_BE0_GLOBAL_SYNC_CONFIG, CDC, id), \
SRIDFVL(VPCDC_GLOBAL_SYNC_TRIGGER, CDC, id), \
SRIDFVL(VPEP_MEM_GLOBAL_PWR_REQ_CNTL, CDC, id), SRIDFVL(VPFE_MEM_PWR_CNTL, CDC, id), \
SRIDFVL(VPBE_MEM_PWR_CNTL, CDC, id)
#define CDC_FLIED_LIST_VPE10(post_fix) \
#define CDC_FE_FIELD_LIST_VPE10(post_fix) \
SFRB(VPDPP0_CLK_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \
SFRB(VPMPC_CLK_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \
SFRB(VPOPP_CLK_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \
@@ -74,14 +73,6 @@ extern "C" {
SFRB(VIEWPORT_Y_START_C_FE0, VPCDC_FE0_VIEWPORT_START_C_CONFIG, post_fix), \
SFRB(VIEWPORT_WIDTH_C_FE0, VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG, post_fix), \
SFRB(VIEWPORT_HEIGHT_C_FE0, VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG, post_fix), \
SFRB(VPCDC_BE0_P2B_XBAR_SEL0, VPCDC_BE0_P2B_CONFIG, post_fix), \
SFRB(VPCDC_BE0_P2B_XBAR_SEL1, VPCDC_BE0_P2B_CONFIG, post_fix), \
SFRB(VPCDC_BE0_P2B_XBAR_SEL2, VPCDC_BE0_P2B_CONFIG, post_fix), \
SFRB(VPCDC_BE0_P2B_XBAR_SEL3, VPCDC_BE0_P2B_CONFIG, post_fix), \
SFRB(VPCDC_BE0_P2B_FORMAT_SEL, VPCDC_BE0_P2B_CONFIG, post_fix), \
SFRB(BE0_VUPDATE_OFFSET, VPCDC_BE0_GLOBAL_SYNC_CONFIG, post_fix), \
SFRB(BE0_VUPDATE_WIDTH, VPCDC_BE0_GLOBAL_SYNC_CONFIG, post_fix), \
SFRB(BE0_VREADY_OFFSET, VPCDC_BE0_GLOBAL_SYNC_CONFIG, post_fix), \
SFRB(VPBE_GS_TRIG, VPCDC_GLOBAL_SYNC_TRIGGER, post_fix), \
SFRB(VPFE_VR_STATUS, VPCDC_VREADY_STATUS, post_fix), \
SFRB(MEM_GLOBAL_PWR_REQ_DIS, VPEP_MEM_GLOBAL_PWR_REQ_CNTL, post_fix), \
@@ -95,7 +86,7 @@ extern "C" {
SFRB(VPBE0_MEM_PWR_DIS, VPBE_MEM_PWR_CNTL, post_fix)
/* define all structure register variables below */
#define CDC_REG_VARIABLE_LIST_VPE10 \
#define CDC_FE_REG_VARIABLE_LIST_VPE10 \
reg_id_val VPEP_MGCG_CNTL; \
reg_id_val VPCDC_SOFT_RESET; \
reg_id_val VPCDC_FE0_SURFACE_CONFIG; \
@@ -104,14 +95,12 @@ extern "C" {
reg_id_val VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG; \
reg_id_val VPCDC_FE0_VIEWPORT_START_C_CONFIG; \
reg_id_val VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG; \
reg_id_val VPCDC_BE0_P2B_CONFIG; \
reg_id_val VPCDC_BE0_GLOBAL_SYNC_CONFIG; \
reg_id_val VPCDC_GLOBAL_SYNC_TRIGGER; \
reg_id_val VPEP_MEM_GLOBAL_PWR_REQ_CNTL; \
reg_id_val VPFE_MEM_PWR_CNTL; \
reg_id_val VPBE_MEM_PWR_CNTL;
#define CDC_FIELD_VARIABLE_LIST_VPE10(type) \
#define CDC_FE_FIELD_VARIABLE_LIST_VPE10(type) \
type VPDPP0_CLK_GATE_DIS; \
type VPMPC_CLK_GATE_DIS; \
type VPOPP_CLK_GATE_DIS; \
@@ -137,14 +126,6 @@ extern "C" {
type VIEWPORT_Y_START_C_FE0; \
type VIEWPORT_WIDTH_C_FE0; \
type VIEWPORT_HEIGHT_C_FE0; \
type VPCDC_BE0_P2B_XBAR_SEL0; \
type VPCDC_BE0_P2B_XBAR_SEL1; \
type VPCDC_BE0_P2B_XBAR_SEL2; \
type VPCDC_BE0_P2B_XBAR_SEL3; \
type VPCDC_BE0_P2B_FORMAT_SEL; \
type BE0_VUPDATE_OFFSET; \
type BE0_VUPDATE_WIDTH; \
type BE0_VREADY_OFFSET; \
type VPBE_GS_TRIG; \
type VPFE_VR_STATUS; \
type MEM_GLOBAL_PWR_REQ_DIS; \
@@ -157,45 +138,37 @@ extern "C" {
type VPBE0_MEM_PWR_STATE; \
type VPBE0_MEM_PWR_DIS;
struct vpe10_cdc_registers {
CDC_REG_VARIABLE_LIST_VPE10
struct vpe10_cdc_fe_registers {
CDC_FE_REG_VARIABLE_LIST_VPE10
};
struct vpe10_cdc_shift {
CDC_FIELD_VARIABLE_LIST_VPE10(uint8_t)
struct vpe10_cdc_fe_shift {
CDC_FE_FIELD_VARIABLE_LIST_VPE10(uint8_t)
};
struct vpe10_cdc_mask {
CDC_FIELD_VARIABLE_LIST_VPE10(uint32_t)
struct vpe10_cdc_fe_mask {
CDC_FE_FIELD_VARIABLE_LIST_VPE10(uint32_t)
};
struct vpe10_cdc {
struct cdc base; // base class, must be the first field
struct vpe10_cdc_registers *regs;
const struct vpe10_cdc_shift *shift;
const struct vpe10_cdc_mask *mask;
struct vpe10_cdc_fe {
struct cdc_fe base; // base class, must be the first field
struct vpe10_cdc_fe_registers *regs;
const struct vpe10_cdc_fe_shift *shift;
const struct vpe10_cdc_fe_mask *mask;
};
void vpe10_construct_cdc(struct vpe_priv *vpe_priv, struct cdc *cdc);
void vpe10_construct_cdc_fe(struct vpe_priv *vpe_priv, struct cdc_fe *cdc_fe);
bool vpe10_cdc_check_input_format(struct cdc *cdc, enum vpe_surface_pixel_format format);
bool vpe10_cdc_check_input_format(struct cdc_fe *cdc_fe, enum vpe_surface_pixel_format format);
bool vpe10_cdc_check_output_format(struct cdc *cdc, enum vpe_surface_pixel_format format);
void vpe10_cdc_program_surface_config(struct cdc *cdc, enum vpe_surface_pixel_format format,
void vpe10_cdc_program_surface_config(struct cdc_fe *cdc_fe, enum vpe_surface_pixel_format format,
enum vpe_rotation_angle rotation, bool horizontal_mirror, enum vpe_swizzle_mode_values swizzle);
void vpe10_cdc_program_crossbar_config(struct cdc *cdc, enum vpe_surface_pixel_format format);
void vpe10_cdc_program_global_sync(
struct cdc *cdc, uint32_t vupdate_offset, uint32_t vupdate_width, uint32_t vready_offset);
void vpe10_cdc_program_p2b_config(struct cdc *cdc, enum vpe_surface_pixel_format format,
enum vpe_swizzle_mode_values swizzle, const struct vpe_rect *viewport);
void vpe10_cdc_program_crossbar_config(struct cdc_fe *cdc_fe, enum vpe_surface_pixel_format format);
/***** segment register programming *****/
void vpe10_cdc_program_viewport(
struct cdc *cdc, const struct vpe_rect *viewport, const struct vpe_rect *viewport_c);
struct cdc_fe *cdc_fe, const struct vpe_rect *viewport, const struct vpe_rect *viewport_c);
#ifdef __cplusplus
}

3
src/amd/vpelib/src/chip/vpe10/inc/vpe10_resource.h
View File

@@ -78,7 +78,8 @@ struct mpc *vpe10_mpc_create(struct vpe_priv *vpe_priv, int inst);
struct dpp *vpe10_dpp_create(struct vpe_priv *vpe_priv, int inst);
struct cdc *vpe10_cdc_create(struct vpe_priv *vpe_priv, int inst);
struct cdc_fe *vpe10_cdc_fe_create(struct vpe_priv *vpe_priv, int inst);
struct cdc_be *vpe10_cdc_be_create(struct vpe_priv *vpe_priv, int inst);
#ifdef __cplusplus
}

145
src/amd/vpelib/src/chip/vpe10/vpe10_cdc_be.c Normal file
View File

@@ -0,0 +1,145 @@
/* Copyright 2024 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "common.h"
#include "vpe_priv.h"
#include "vpe10_cdc_be.h"
#include "reg_helper.h"
#define CTX_BASE cdc_be
#define CTX vpe10_cdc_be
enum mux_sel {
MUX_SEL_ALPHA = 0,
MUX_SEL_Y_G = 1,
MUX_SEL_CB_B = 2,
MUX_SEL_CR_R = 3
};
static struct cdc_be_funcs cdc_be_func = {
.check_output_format = vpe10_cdc_check_output_format,
.program_global_sync = vpe10_cdc_program_global_sync,
.program_p2b_config = vpe10_cdc_program_p2b_config,
};
void vpe10_construct_cdc_be(struct vpe_priv *vpe_priv, struct cdc_be *cdc_be)
{
cdc_be->vpe_priv = vpe_priv;
cdc_be->funcs = &cdc_be_func;
}
bool vpe10_cdc_check_output_format(struct cdc_be *cdc_be, enum vpe_surface_pixel_format format)
{
if (vpe_is_32bit_packed_rgb(format))
return true;
if (vpe_is_fp16(format))
return true;
return false;
}
void vpe10_cdc_program_global_sync(
struct cdc_be *cdc_be, uint32_t vupdate_offset, uint32_t vupdate_width, uint32_t vready_offset)
{
PROGRAM_ENTRY();
REG_SET_3(VPCDC_BE0_GLOBAL_SYNC_CONFIG, 0, BE0_VUPDATE_OFFSET, vupdate_offset,
BE0_VUPDATE_WIDTH, vupdate_width, BE0_VREADY_OFFSET, vready_offset);
}
void vpe10_cdc_program_p2b_config(struct cdc_be *cdc_be, enum vpe_surface_pixel_format format,
enum vpe_swizzle_mode_values swizzle, const struct vpe_rect *viewport)
{
uint32_t bar_sel0 = (uint32_t)MUX_SEL_CB_B;
uint32_t bar_sel1 = (uint32_t)MUX_SEL_Y_G;
uint32_t bar_sel2 = (uint32_t)MUX_SEL_CR_R;
uint32_t bar_sel3 = (uint32_t)MUX_SEL_ALPHA;
uint32_t p2b_format_sel = 0;
PROGRAM_ENTRY();
switch (format) {
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888:
p2b_format_sel = 0;
break;
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102:
p2b_format_sel = 1;
break;
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F:
p2b_format_sel = 2;
break;
default:
VPE_ASSERT(0);
break;
}
switch (format) {
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F:
bar_sel3 = (uint32_t)MUX_SEL_CR_R;
bar_sel2 = (uint32_t)MUX_SEL_Y_G;
bar_sel1 = (uint32_t)MUX_SEL_CB_B;
bar_sel0 = (uint32_t)MUX_SEL_ALPHA;
break;
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
bar_sel3 = (uint32_t)MUX_SEL_ALPHA;
bar_sel2 = (uint32_t)MUX_SEL_CB_B;
bar_sel1 = (uint32_t)MUX_SEL_Y_G;
bar_sel0 = (uint32_t)MUX_SEL_CR_R;
break;
case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F:
bar_sel3 = (uint32_t)MUX_SEL_CB_B;
bar_sel2 = (uint32_t)MUX_SEL_Y_G;
bar_sel1 = (uint32_t)MUX_SEL_CR_R;
bar_sel0 = (uint32_t)MUX_SEL_ALPHA;
break;
default:
break;
}
REG_SET_5(VPCDC_BE0_P2B_CONFIG, 0, VPCDC_BE0_P2B_XBAR_SEL0, bar_sel0, VPCDC_BE0_P2B_XBAR_SEL1,
bar_sel1, VPCDC_BE0_P2B_XBAR_SEL2, bar_sel2, VPCDC_BE0_P2B_XBAR_SEL3, bar_sel3,
VPCDC_BE0_P2B_FORMAT_SEL, p2b_format_sel);
}

125
src/amd/vpelib/src/chip/vpe10/vpe10_cdc.c → src/amd/vpelib/src/chip/vpe10/vpe10_cdc_fe.c
View File

@@ -1,4 +1,4 @@
/* Copyright 2022 Advanced Micro Devices, Inc.
/* Copyright 2024 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -24,11 +24,11 @@
#include "common.h"
#include "vpe_priv.h"
#include "vpe10_cdc.h"
#include "vpe10_cdc_fe.h"
#include "reg_helper.h"
#define CTX_BASE cdc
#define CTX vpe10_cdc
#define CTX_BASE cdc_fe
#define CTX vpe10_cdc_fe
enum mux_sel {
MUX_SEL_ALPHA = 0,
@@ -37,24 +37,20 @@ enum mux_sel {
MUX_SEL_CR_R = 3
};
static struct cdc_funcs cdc_func = {
.check_input_format = vpe10_cdc_check_input_format,
.check_output_format = vpe10_cdc_check_output_format,
static struct cdc_fe_funcs cdc_fe_func = {
.check_input_format = vpe10_cdc_check_input_format,
.program_surface_config = vpe10_cdc_program_surface_config,
.program_crossbar_config = vpe10_cdc_program_crossbar_config,
.program_global_sync = vpe10_cdc_program_global_sync,
.program_p2b_config = vpe10_cdc_program_p2b_config,
.program_viewport = vpe10_cdc_program_viewport,
};
void vpe10_construct_cdc(struct vpe_priv *vpe_priv, struct cdc *cdc)
void vpe10_construct_cdc_fe(struct vpe_priv *vpe_priv, struct cdc_fe *cdc_fe)
{
cdc->vpe_priv = vpe_priv;
cdc->funcs = &cdc_func;
cdc_fe->vpe_priv = vpe_priv;
cdc_fe->funcs = &cdc_fe_func;
}
bool vpe10_cdc_check_input_format(struct cdc *cdc, enum vpe_surface_pixel_format format)
bool vpe10_cdc_check_input_format(struct cdc_fe *cdc_fe, enum vpe_surface_pixel_format format)
{
if (vpe_is_32bit_packed_rgb(format))
return true;
@@ -70,17 +66,7 @@ bool vpe10_cdc_check_input_format(struct cdc *cdc, enum vpe_surface_pixel_format
return false;
}
bool vpe10_cdc_check_output_format(struct cdc *cdc, enum vpe_surface_pixel_format format)
{
if (vpe_is_32bit_packed_rgb(format))
return true;
if (vpe_is_fp16(format))
return true;
return false;
}
void vpe10_cdc_program_surface_config(struct cdc *cdc, enum vpe_surface_pixel_format format,
void vpe10_cdc_program_surface_config(struct cdc_fe *cdc_fe, enum vpe_surface_pixel_format format,
enum vpe_rotation_angle rotation, bool horizontal_mirror, enum vpe_swizzle_mode_values swizzle)
{
uint32_t rotation_angle = 0, surface_linear;
@@ -184,7 +170,7 @@ void vpe10_cdc_program_surface_config(struct cdc *cdc, enum vpe_surface_pixel_fo
PIX_SURFACE_LINEAR_FE0, surface_linear);
}
void vpe10_cdc_program_crossbar_config(struct cdc *cdc, enum vpe_surface_pixel_format format)
void vpe10_cdc_program_crossbar_config(struct cdc_fe *cdc_fe, enum vpe_surface_pixel_format format)
{
uint32_t alpha_bar = (uint32_t)MUX_SEL_ALPHA;
uint32_t green_bar = (uint32_t)MUX_SEL_Y_G;
@@ -211,94 +197,9 @@ void vpe10_cdc_program_crossbar_config(struct cdc *cdc, enum vpe_surface_pixel_f
blue_bar);
}
void vpe10_cdc_program_global_sync(
struct cdc *cdc, uint32_t vupdate_offset, uint32_t vupdate_width, uint32_t vready_offset)
{
PROGRAM_ENTRY();
REG_SET_3(VPCDC_BE0_GLOBAL_SYNC_CONFIG, 0, BE0_VUPDATE_OFFSET, vupdate_offset,
BE0_VUPDATE_WIDTH, vupdate_width, BE0_VREADY_OFFSET, vready_offset);
}
void vpe10_cdc_program_p2b_config(struct cdc *cdc, enum vpe_surface_pixel_format format,
enum vpe_swizzle_mode_values swizzle, const struct vpe_rect *viewport)
{
uint32_t bar_sel0 = (uint32_t)MUX_SEL_CB_B;
uint32_t bar_sel1 = (uint32_t)MUX_SEL_Y_G;
uint32_t bar_sel2 = (uint32_t)MUX_SEL_CR_R;
uint32_t bar_sel3 = (uint32_t)MUX_SEL_ALPHA;
uint32_t p2b_format_sel = 0;
PROGRAM_ENTRY();
switch (format) {
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888:
p2b_format_sel = 0;
break;
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102:
p2b_format_sel = 1;
break;
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F:
p2b_format_sel = 2;
break;
default:
VPE_ASSERT(0);
break;
}
switch (format) {
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F:
bar_sel3 = (uint32_t)MUX_SEL_CR_R;
bar_sel2 = (uint32_t)MUX_SEL_Y_G;
bar_sel1 = (uint32_t)MUX_SEL_CB_B;
bar_sel0 = (uint32_t)MUX_SEL_ALPHA;
break;
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
bar_sel3 = (uint32_t)MUX_SEL_ALPHA;
bar_sel2 = (uint32_t)MUX_SEL_CB_B;
bar_sel1 = (uint32_t)MUX_SEL_Y_G;
bar_sel0 = (uint32_t)MUX_SEL_CR_R;
break;
case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102:
case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F:
bar_sel3 = (uint32_t)MUX_SEL_CB_B;
bar_sel2 = (uint32_t)MUX_SEL_Y_G;
bar_sel1 = (uint32_t)MUX_SEL_CR_R;
bar_sel0 = (uint32_t)MUX_SEL_ALPHA;
break;
default:
break;
}
REG_SET_5(VPCDC_BE0_P2B_CONFIG, 0, VPCDC_BE0_P2B_XBAR_SEL0, bar_sel0, VPCDC_BE0_P2B_XBAR_SEL1,
bar_sel1, VPCDC_BE0_P2B_XBAR_SEL2, bar_sel2, VPCDC_BE0_P2B_XBAR_SEL3, bar_sel3,
VPCDC_BE0_P2B_FORMAT_SEL, p2b_format_sel);
}
/** segment specific */
void vpe10_cdc_program_viewport(
struct cdc *cdc, const struct vpe_rect *viewport, const struct vpe_rect *viewport_c)
struct cdc_fe *cdc_fe, const struct vpe_rect *viewport, const struct vpe_rect *viewport_c)
{
PROGRAM_ENTRY();

12
src/amd/vpelib/src/chip/vpe10/vpe10_cmd_builder.c
View File

@@ -284,18 +284,6 @@ static void get_np_and_subop(struct vpe_priv *vpe_priv, struct vpe_cmd_info *cmd
header->nps0 = VPE_PLANE_CFG_TWO_PLANES;
else
header->nps0 = VPE_PLANE_CFG_ONE_PLANE;
} else if (cmd_info->num_inputs == 2) {
if (vpe_is_dual_plane_format(
vpe_priv->stream_ctx[cmd_info->inputs[0].stream_idx].stream.surface_info.format))
header->nps0 = VPE_PLANE_CFG_TWO_PLANES;
else
header->nps0 = VPE_PLANE_CFG_ONE_PLANE;
if (vpe_is_dual_plane_format(
vpe_priv->stream_ctx[cmd_info->inputs[1].stream_idx].stream.surface_info.format))
header->nps1 = VPE_PLANE_CFG_TWO_PLANES;
else
header->nps1 = VPE_PLANE_CFG_ONE_PLANE;
} else {
header->nps0 = 0;
header->nps1 = 0;

93
src/amd/vpelib/src/chip/vpe10/vpe10_resource.c
View File

@@ -27,7 +27,8 @@
#include "vpe10_resource.h"
#include "vpe10_cmd_builder.h"
#include "vpe10_vpec.h"
#include "vpe10_cdc.h"
#include "vpe10_cdc_fe.h"
#include "vpe10_cdc_be.h"
#include "vpe10_dpp.h"
#include "vpe10_mpc.h"
#include "vpe10_opp.h"
@@ -76,14 +77,23 @@
.block##_##reg_name = {BASE(reg##block##_##reg_name##_BASE_IDX) + reg##block##_##reg_name, \
reg##block##_##reg_name##_##DEFAULT, reg##block##_##reg_name##_##DEFAULT, false}
/***************** CDC registers ****************/
#define cdc_regs(id) [id] = {CDC_REG_LIST_VPE10(id)}
/***************** CDC FE registers ****************/
#define cdc_fe_regs(id) [id] = {CDC_FE_REG_LIST_VPE10(id)}
static struct vpe10_cdc_registers cdc_regs[] = {cdc_regs(0)};
static struct vpe10_cdc_fe_registers cdc_fe_regs[] = {cdc_fe_regs(0)};
static const struct vpe10_cdc_shift cdc_shift = {CDC_FLIED_LIST_VPE10(__SHIFT)};
static const struct vpe10_cdc_fe_shift cdc_fe_shift = {CDC_FE_FIELD_LIST_VPE10(__SHIFT)};
static const struct vpe10_cdc_mask cdc_mask = {CDC_FLIED_LIST_VPE10(_MASK)};
static const struct vpe10_cdc_fe_mask cdc_fe_mask = {CDC_FE_FIELD_LIST_VPE10(_MASK)};
/***************** CDC BE registers ****************/
#define cdc_be_regs(id) [id] = {CDC_BE_REG_LIST_VPE10(id)}
static struct vpe10_cdc_be_registers cdc_be_regs[] = {cdc_be_regs(0)};
static const struct vpe10_cdc_be_shift cdc_be_shift = {CDC_BE_FIELD_LIST_VPE10(__SHIFT)};
static const struct vpe10_cdc_be_mask cdc_be_mask = {CDC_BE_FIELD_LIST_VPE10(_MASK)};
/***************** DPP registers ****************/
#define dpp_regs(id) [id] = {DPP_REG_LIST_VPE10(id)}
@@ -125,6 +135,7 @@ static struct vpe_caps caps = {
.num_opp = 1,
.num_mpc_3dlut = 1,
.num_queue = 8,
.num_cdc_be = 1,
},
.color_caps = {.dpp =
{
@@ -276,20 +287,36 @@ static struct vpe_cap_funcs cap_funcs =
.get_dcc_compression_input_cap = vpe10_get_dcc_compression_input_cap
};
struct cdc *vpe10_cdc_create(struct vpe_priv *vpe_priv, int inst)
struct cdc_fe *vpe10_cdc_fe_create(struct vpe_priv *vpe_priv, int inst)
{
struct vpe10_cdc *vpe10_cdc = vpe_zalloc(sizeof(struct vpe10_cdc));
struct vpe10_cdc_fe *vpe10_cdc_fe = vpe_zalloc(sizeof(struct vpe10_cdc_fe));
if (!vpe10_cdc)
if (!vpe10_cdc_fe)
return NULL;
vpe10_construct_cdc(vpe_priv, &vpe10_cdc->base);
vpe10_construct_cdc_fe(vpe_priv, &vpe10_cdc_fe->base);
vpe10_cdc->regs = &cdc_regs[inst];
vpe10_cdc->mask = &cdc_mask;
vpe10_cdc->shift = &cdc_shift;
vpe10_cdc_fe->regs = &cdc_fe_regs[inst];
vpe10_cdc_fe->mask = &cdc_fe_mask;
vpe10_cdc_fe->shift = &cdc_fe_shift;
return &vpe10_cdc->base;
return &vpe10_cdc_fe->base;
}
struct cdc_be *vpe10_cdc_be_create(struct vpe_priv *vpe_priv, int inst)
{
struct vpe10_cdc_be *vpe10_cdc_be = vpe_zalloc(sizeof(struct vpe10_cdc_be));
if (!vpe10_cdc_be)
return NULL;
vpe10_construct_cdc_be(vpe_priv, &vpe10_cdc_be->base);
vpe10_cdc_be->regs = &cdc_be_regs[inst];
vpe10_cdc_be->mask = &cdc_be_mask;
vpe10_cdc_be->shift = &cdc_be_shift;
return &vpe10_cdc_be->base;
}
struct dpp *vpe10_dpp_create(struct vpe_priv *vpe_priv, int inst)
@@ -349,8 +376,8 @@ enum vpe_status vpe10_construct_resource(struct vpe_priv *vpe_priv, struct resou
vpe10_construct_vpec(vpe_priv, &res->vpec);
res->cdc[0] = vpe10_cdc_create(vpe_priv, 0);
if (!res->cdc[0])
res->cdc_fe[0] = vpe10_cdc_fe_create(vpe_priv, 0);
if (!res->cdc_fe[0])
goto err;
res->dpp[0] = vpe10_dpp_create(vpe_priv, 0);
@@ -361,6 +388,10 @@ enum vpe_status vpe10_construct_resource(struct vpe_priv *vpe_priv, struct resou
if (!res->mpc[0])
goto err;
res->cdc_be[0] = vpe10_cdc_be_create(vpe_priv, 0);
if (!res->cdc_be[0])
goto err;
res->opp[0] = vpe10_opp_create(vpe_priv, 0);
if (!res->opp[0])
goto err;
@@ -398,9 +429,9 @@ err:
void vpe10_destroy_resource(struct vpe_priv *vpe_priv, struct resource *res)
{
if (res->cdc[0] != NULL) {
vpe_free(container_of(res->cdc[0], struct vpe10_cdc, base));
res->cdc[0] = NULL;
if (res->cdc_fe[0] != NULL) {
vpe_free(container_of(res->cdc_fe[0], struct vpe10_cdc_fe, base));
res->cdc_fe[0] = NULL;
}
if (res->dpp[0] != NULL) {
@@ -413,6 +444,11 @@ void vpe10_destroy_resource(struct vpe_priv *vpe_priv, struct resource *res)
res->mpc[0] = NULL;
}
if (res->cdc_be[0] != NULL) {
vpe_free(container_of(res->cdc_be[0], struct vpe10_cdc_be, base));
res->cdc_be[0] = NULL;
}
if (res->opp[0] != NULL) {
vpe_free(container_of(res->opp[0], struct vpe10_opp, base));
res->opp[0] = NULL;
@@ -715,7 +751,7 @@ int32_t vpe10_program_frontend(struct vpe_priv *vpe_priv, uint32_t pipe_idx, uin
struct vpe_cmd_input *cmd_input = &cmd_info->inputs[cmd_input_idx];
struct stream_ctx *stream_ctx = &vpe_priv->stream_ctx[cmd_input->stream_idx];
struct vpe_surface_info *surface_info = &stream_ctx->stream.surface_info;
struct cdc *cdc = vpe_priv->resource.cdc[pipe_idx];
struct cdc_fe *cdc_fe = vpe_priv->resource.cdc_fe[pipe_idx];
struct dpp *dpp = vpe_priv->resource.dpp[pipe_idx];
struct mpc *mpc = vpe_priv->resource.mpc[pipe_idx];
enum input_csc_select select = INPUT_CSC_SELECT_BYPASS;
@@ -735,10 +771,11 @@ int32_t vpe10_program_frontend(struct vpe_priv *vpe_priv, uint32_t pipe_idx, uin
/* start front-end programming that can be shared among segments */
vpe_priv->fe_cb_ctx.stream_sharing = true;
cdc->funcs->program_surface_config(cdc, surface_info->format, stream_ctx->stream.rotation,
cdc_fe->funcs->program_surface_config(cdc_fe, surface_info->format,
stream_ctx->stream.rotation,
// set to false as h_mirror is not supported by input, only supported in output
false, surface_info->swizzle);
cdc->funcs->program_crossbar_config(cdc, surface_info->format);
cdc_fe->funcs->program_crossbar_config(cdc_fe, surface_info->format);
dpp->funcs->program_cnv(dpp, surface_info->format, vpe_priv->expansion_mode);
if (stream_ctx->bias_scale)
@@ -795,8 +832,8 @@ int32_t vpe10_program_frontend(struct vpe_priv *vpe_priv, uint32_t pipe_idx, uin
vpe_priv->fe_cb_ctx.stream_op_sharing = false;
vpe_priv->fe_cb_ctx.cmd_type = VPE_CMD_TYPE_COMPOSITING;
cdc->funcs->program_viewport(
cdc, &cmd_input->scaler_data.viewport, &cmd_input->scaler_data.viewport_c);
cdc_fe->funcs->program_viewport(
cdc_fe, &cmd_input->scaler_data.viewport, &cmd_input->scaler_data.viewport_c);
dpp->funcs->set_segment_scaler(dpp, &cmd_input->scaler_data);
@@ -811,7 +848,7 @@ int32_t vpe10_program_backend(
struct output_ctx *output_ctx = &vpe_priv->output_ctx;
struct vpe_surface_info *surface_info = &vpe_priv->output_ctx.surface;
struct cdc *cdc = vpe_priv->resource.cdc[pipe_idx];
struct cdc_be *cdc_be = vpe_priv->resource.cdc_be[pipe_idx];
struct opp *opp = vpe_priv->resource.opp[pipe_idx];
struct mpc *mpc = vpe_priv->resource.mpc[pipe_idx];
@@ -831,9 +868,9 @@ int32_t vpe10_program_backend(
/* start back-end programming that can be shared among segments */
vpe_priv->be_cb_ctx.share = true;
cdc->funcs->program_p2b_config(
cdc, surface_info->format, surface_info->swizzle, &output_ctx->target_rect);
cdc->funcs->program_global_sync(cdc, VPE10_CDC_VUPDATE_OFFSET_DEFAULT,
cdc_be->funcs->program_p2b_config(
cdc_be, surface_info->format, surface_info->swizzle, &output_ctx->target_rect);
cdc_be->funcs->program_global_sync(cdc_be, VPE10_CDC_VUPDATE_OFFSET_DEFAULT,
VPE10_CDC_VUPDATE_WIDTH_DEFAULT, VPE10_CDC_VREADY_OFFSET_DEFAULT);
mpc->funcs->set_output_transfer_func(mpc, output_ctx);

23
src/amd/vpelib/src/chip/vpe11/vpe11_resource.c
View File

@@ -28,7 +28,8 @@
#include "vpe10_resource.h"
#include "vpe11_cmd_builder.h"
#include "vpe10_vpec.h"
#include "vpe10_cdc.h"
#include "vpe10_cdc_be.h"
#include "vpe10_cdc_fe.h"
#include "vpe10_dpp.h"
#include "vpe10_mpc.h"
#include "vpe10_opp.h"
@@ -77,6 +78,7 @@ static struct vpe_caps caps = {
.num_opp = 1,
.num_mpc_3dlut = 1,
.num_queue = 8,
.num_cdc_be = 1,
},
.color_caps = {.dpp =
{
@@ -156,8 +158,8 @@ enum vpe_status vpe11_construct_resource(struct vpe_priv *vpe_priv, struct resou
vpe10_construct_vpec(vpe_priv, &res->vpec);
res->cdc[0] = vpe10_cdc_create(vpe_priv, 0);
if (!res->cdc[0])
res->cdc_fe[0] = vpe10_cdc_fe_create(vpe_priv, 0);
if (!res->cdc_fe[0])
goto err;
res->dpp[0] = vpe10_dpp_create(vpe_priv, 0);
@@ -168,6 +170,10 @@ enum vpe_status vpe11_construct_resource(struct vpe_priv *vpe_priv, struct resou
if (!res->mpc[0])
goto err;
res->cdc_be[0] = vpe10_cdc_be_create(vpe_priv, 0);
if (!res->cdc_be[0])
goto err;
res->opp[0] = vpe10_opp_create(vpe_priv, 0);
if (!res->opp[0])
goto err;
@@ -205,9 +211,9 @@ err:
void vpe11_destroy_resource(struct vpe_priv *vpe_priv, struct resource *res)
{
if (res->cdc[0] != NULL) {
vpe_free(container_of(res->cdc[0], struct vpe10_cdc, base));
res->cdc[0] = NULL;
if (res->cdc_fe[0] != NULL) {
vpe_free(container_of(res->cdc_fe[0], struct vpe10_cdc_fe, base));
res->cdc_fe[0] = NULL;
}
if (res->dpp[0] != NULL) {
@@ -220,6 +226,11 @@ void vpe11_destroy_resource(struct vpe_priv *vpe_priv, struct resource *res)
res->mpc[0] = NULL;
}
if (res->cdc_be[0] != NULL) {
vpe_free(container_of(res->cdc_be[0], struct vpe10_cdc_be, base));
res->cdc_be[0] = NULL;
}
if (res->opp[0] != NULL) {
vpe_free(container_of(res->opp[0], struct vpe10_opp, base));
res->opp[0] = NULL;

20
src/amd/vpelib/src/core/common.c
View File

@@ -334,15 +334,15 @@ enum vpe_status vpe_check_output_support(struct vpe *vpe, const struct vpe_build
struct vpe_priv *vpe_priv = container_of(vpe, struct vpe_priv, pub);
struct vpec *vpec;
struct dpp *dpp;
struct cdc *cdc;
struct cdc_be *cdc_be;
const struct vpe_surface_info *surface_info = &param->dst_surface;
struct vpe_dcc_surface_param params;
struct vpe_surface_dcc_cap cap;
bool support;
vpec = &vpe_priv->resource.vpec;
dpp = vpe_priv->resource.dpp[0];
cdc = vpe_priv->resource.cdc[0];
vpec = &vpe_priv->resource.vpec;
dpp = vpe_priv->resource.dpp[0];
cdc_be = vpe_priv->resource.cdc_be[0];
// swizzle mode
support = vpec->funcs->check_swmode_support(vpec, surface_info->swizzle);
@@ -409,7 +409,7 @@ enum vpe_status vpe_check_output_support(struct vpe *vpe, const struct vpe_build
}
// pixel format
support = cdc->funcs->check_output_format(cdc, surface_info->format);
support = cdc_be->funcs->check_output_format(cdc_be, surface_info->format);
if (!support) {
vpe_log("output pixel format not supported %d\n", (int)surface_info->format);
return VPE_STATUS_PIXEL_FORMAT_NOT_SUPPORTED;
@@ -435,7 +435,7 @@ enum vpe_status vpe_check_input_support(struct vpe *vpe, const struct vpe_stream
struct vpe_priv *vpe_priv = container_of(vpe, struct vpe_priv, pub);
struct vpec *vpec;
struct dpp *dpp;
struct cdc *cdc;
struct cdc_fe *cdc_fe;
const struct vpe_surface_info *surface_info = &stream->surface_info;
struct vpe_dcc_surface_param params;
struct vpe_surface_dcc_cap cap;
@@ -444,9 +444,9 @@ enum vpe_status vpe_check_input_support(struct vpe *vpe, const struct vpe_stream
bool use_adj = vpe_use_csc_adjust(&stream->color_adj);
enum vpe_status status = VPE_STATUS_OK;
vpec = &vpe_priv->resource.vpec;
dpp = vpe_priv->resource.dpp[0];
cdc = vpe_priv->resource.cdc[0];
vpec = &vpe_priv->resource.vpec;
dpp = vpe_priv->resource.dpp[0];
cdc_fe = vpe_priv->resource.cdc_fe[0];
// swizzle mode
support = vpec->funcs->check_swmode_support(vpec, surface_info->swizzle);
@@ -513,7 +513,7 @@ enum vpe_status vpe_check_input_support(struct vpe *vpe, const struct vpe_stream
}
// pixel format
support = cdc->funcs->check_input_format(cdc, surface_info->format);
support = cdc_fe->funcs->check_input_format(cdc_fe, surface_info->format);
if (!support) {
vpe_log("input pixel format not supported %d\n", (int)surface_info->format);
return VPE_STATUS_PIXEL_FORMAT_NOT_SUPPORTED;

42
src/amd/vpelib/src/core/inc/cdc.h
View File

@@ -30,37 +30,51 @@
extern "C" {
#endif
struct cdc;
struct cdc_fe;
struct cdc_be;
struct vpe_priv;
/** note: all program_* functions shall return number of config packet created */
struct cdc_funcs {
bool (*check_input_format)(struct cdc *cdc, enum vpe_surface_pixel_format format);
bool (*check_output_format)(struct cdc *cdc, enum vpe_surface_pixel_format format);
struct cdc_fe_funcs {
bool (*check_input_format)(struct cdc_fe *cdc_fe, enum vpe_surface_pixel_format format);
/** non segment specific */
void (*program_surface_config)(struct cdc *cdc, enum vpe_surface_pixel_format format,
void (*program_surface_config)(struct cdc_fe *cdc_fe, enum vpe_surface_pixel_format format,
enum vpe_rotation_angle rotation, bool horizontal_mirror,
enum vpe_swizzle_mode_values swizzle);
void (*program_crossbar_config)(struct cdc *cdc, enum vpe_surface_pixel_format format);
void (*program_crossbar_config)(struct cdc_fe *cdc_fe, enum vpe_surface_pixel_format format);
void (*program_global_sync)(
struct cdc *cdc, uint32_t vupdate_offset, uint32_t vupdate_width, uint32_t vready_offset);
void (*program_global_sync)(struct cdc_fe *cdc_fe, uint32_t vupdate_offset,
uint32_t vupdate_width, uint32_t vready_offset);
void (*program_p2b_config)(struct cdc *cdc, enum vpe_surface_pixel_format format,
void (*program_p2b_config)(struct cdc_fe *cdc_fe, enum vpe_surface_pixel_format format,
enum vpe_swizzle_mode_values swizzle, const struct vpe_rect *viewport);
/** segment specific */
void (*program_viewport)(
struct cdc *cdc, const struct vpe_rect *viewport, const struct vpe_rect *viewport_c);
struct cdc_fe *cdc_fe, const struct vpe_rect *viewport, const struct vpe_rect *viewport_c);
};
struct cdc {
struct cdc_be_funcs {
bool (*check_output_format)(struct cdc_be *cdc_be, enum vpe_surface_pixel_format format);
void (*program_global_sync)(struct cdc_be *cdc_be, uint32_t vupdate_offset,
uint32_t vupdate_width, uint32_t vready_offset);
void (*program_p2b_config)(struct cdc_be *cdc_be, enum vpe_surface_pixel_format format,
enum vpe_swizzle_mode_values swizzle, const struct vpe_rect *viewport);
};
struct cdc_fe {
struct vpe_priv *vpe_priv;
struct cdc_fe_funcs *funcs;
unsigned int inst;
};
struct cdc_be {
struct vpe_priv *vpe_priv;
struct cdc_funcs *funcs;
struct cdc_be_funcs *funcs;
unsigned int inst;
};

7
src/amd/vpelib/src/core/inc/color.h
View File

@@ -169,10 +169,11 @@ struct transfer_func {
};
// the followings are for optimization: skip if no change
bool dirty[MAX_PIPE]; /*< indicate this object is updated or not */
struct config_cache config_cache[MAX_PIPE]; /*< used by the hw hook layer to do the caching */
bool dirty[MAX_INPUT_PIPE]; /*< indicate this object is updated or not */
struct config_cache
config_cache[MAX_INPUT_PIPE]; /*< used by the hw hook layer to do the caching */
struct cache_info cache_info[MAX_PIPE];
struct cache_info cache_info[MAX_INPUT_PIPE];
};
enum color_white_point_type {

2
src/amd/vpelib/src/core/inc/hw_shared.h
View File

@@ -28,7 +28,7 @@
#define MAX_3DLUT 1
#define MAX_PIPE 2
#define MAX_INPUT_PIPE 1
#define MAX_OUTPUT_PIPE 1
#ifdef __cplusplus

9
src/amd/vpelib/src/core/inc/resource.h
View File

@@ -105,10 +105,11 @@ struct resource {
int internal_hdr_normalization;
// vpep components
struct cdc *cdc[MAX_PIPE];
struct dpp *dpp[MAX_PIPE];
struct opp *opp[MAX_PIPE];
struct mpc *mpc[MAX_PIPE];
struct cdc_fe *cdc_fe[MAX_INPUT_PIPE];
struct cdc_be *cdc_be[MAX_OUTPUT_PIPE];
struct dpp *dpp[MAX_INPUT_PIPE];
struct opp *opp[MAX_INPUT_PIPE];
struct mpc *mpc[MAX_INPUT_PIPE];
struct cmd_builder cmd_builder;
};

16
src/amd/vpelib/src/core/inc/vpe_priv.h
View File

@@ -103,7 +103,7 @@ struct vpe_cmd_info {
// input
uint16_t num_inputs;
struct vpe_cmd_input inputs[MAX_PIPE];
struct vpe_cmd_input inputs[MAX_INPUT_PIPE];
// output
uint16_t num_outputs;
@@ -130,11 +130,13 @@ struct stream_ctx {
uint16_t num_segments;
struct segment_ctx *segment_ctx;
uint16_t num_configs[MAX_PIPE]; // shared among same stream
uint16_t num_stream_op_configs[MAX_PIPE][VPE_CMD_TYPE_COUNT]; // shared among same cmd type
// within the same stream
struct config_record configs[MAX_PIPE][MAX_NUM_SAVED_CONFIG];
struct config_record stream_op_configs[MAX_PIPE][VPE_CMD_TYPE_COUNT][MAX_NUM_SAVED_CONFIG];
uint16_t num_configs[MAX_INPUT_PIPE]; // shared among same stream
uint16_t num_stream_op_configs[MAX_INPUT_PIPE][VPE_CMD_TYPE_COUNT];
// shared among same cmd type, within the same stream
struct config_record configs[MAX_INPUT_PIPE][MAX_NUM_SAVED_CONFIG];
struct config_record stream_op_configs[MAX_INPUT_PIPE][VPE_CMD_TYPE_COUNT]
[MAX_NUM_SAVED_CONFIG];
// cached color properties
bool per_pixel_alpha;
@@ -259,7 +261,7 @@ struct vpe_priv {
struct output_ctx output_ctx;
uint16_t num_pipe;
struct pipe_ctx pipe_ctx[MAX_PIPE];
struct pipe_ctx pipe_ctx[MAX_INPUT_PIPE];
// internal temp structure for creating pure BG filling
struct vpe_build_param *dummy_input_param;

6
src/amd/vpelib/src/core/resource.c
View File

@@ -199,7 +199,7 @@ void vpe_free_stream_ctx(struct vpe_priv *vpe_priv)
for (i = 0; i < vpe_priv->num_streams; i++) {
ctx = &vpe_priv->stream_ctx[i];
if (ctx->input_tf) {
for (int j = 0; j < MAX_PIPE; j++)
for (int j = 0; j < MAX_INPUT_PIPE; j++)
CONFIG_CACHE_FREE(ctx->input_tf->config_cache[j]);
vpe_free(ctx->input_tf);
ctx->input_tf = NULL;
@@ -221,14 +221,14 @@ void vpe_free_stream_ctx(struct vpe_priv *vpe_priv)
}
if (ctx->in_shaper_func) {
for (int j = 0; j < MAX_PIPE; j++)
for (int j = 0; j < MAX_INPUT_PIPE; j++)
CONFIG_CACHE_FREE(ctx->in_shaper_func->config_cache[j]);
vpe_free(ctx->in_shaper_func);
ctx->in_shaper_func = NULL;
}
if (ctx->blend_tf) {
for (int j = 0; j < MAX_PIPE; j++)
for (int j = 0; j < MAX_INPUT_PIPE; j++)
CONFIG_CACHE_FREE(ctx->blend_tf->config_cache[j]);
vpe_free(ctx->blend_tf);
ctx->blend_tf = NULL;

2
src/amd/vpelib/src/core/vpelib.c
View File

@@ -686,7 +686,7 @@ enum vpe_status vpe_build_commands(
// copy the param, reset saved configs
for (stream_idx = 0; stream_idx < vpe_priv->num_streams; stream_idx++) {
for (pipe_idx = 0; pipe_idx < MAX_PIPE; pipe_idx++) {
for (pipe_idx = 0; pipe_idx < MAX_INPUT_PIPE; pipe_idx++) {
vpe_priv->stream_ctx[stream_idx].num_configs[pipe_idx] = 0;
for (cmd_type_idx = 0; cmd_type_idx < VPE_CMD_TYPE_COUNT; cmd_type_idx++)
vpe_priv->stream_ctx[stream_idx].num_stream_op_configs[pipe_idx][cmd_type_idx] = 0;