radv: split out a chunk of variant filling code.
This code will have use for copy shaders etc. Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@@ -342,43 +342,19 @@ void radv_shader_variant_destroy(struct radv_device *device,
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free(variant);
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free(variant);
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}
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}
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static
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static void radv_fill_shader_variant(struct radv_device *device,
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struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
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struct radv_shader_variant *variant,
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struct nir_shader *shader,
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struct ac_shader_binary *binary,
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struct radv_pipeline_layout *layout,
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gl_shader_stage stage)
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const union ac_shader_variant_key *key,
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void** code_out,
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unsigned *code_size_out,
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bool dump)
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{
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{
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struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
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variant->code_size = binary->code_size;
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enum radeon_family chip_family = device->instance->physicalDevice.rad_info.family;
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LLVMTargetMachineRef tm;
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if (!variant)
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return NULL;
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struct ac_nir_compiler_options options = {0};
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options.layout = layout;
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if (key)
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options.key = *key;
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struct ac_shader_binary binary;
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options.unsafe_math = env_var_as_boolean("RADV_UNSAFE_MATH", false);
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options.family = chip_family;
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options.chip_class = device->instance->physicalDevice.rad_info.chip_class;
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tm = ac_create_target_machine(chip_family);
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ac_compile_nir_shader(tm, &binary, &variant->config,
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&variant->info, shader, &options, dump);
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LLVMDisposeTargetMachine(tm);
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variant->code_size = binary.code_size;
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bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
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bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
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unsigned vgpr_comp_cnt = 0;
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unsigned vgpr_comp_cnt = 0;
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if (scratch_enabled)
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if (scratch_enabled)
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radv_finishme("shader scratch space");
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radv_finishme("shader scratch space");
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switch (shader->stage) {
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switch (stage) {
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case MESA_SHADER_VERTEX:
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case MESA_SHADER_VERTEX:
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variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
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variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
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S_00B12C_SCRATCH_EN(scratch_enabled);
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S_00B12C_SCRATCH_EN(scratch_enabled);
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@@ -407,13 +383,47 @@ struct radv_shader_variant *radv_shader_variant_create(struct radv_device *devic
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S_00B848_DX10_CLAMP(1) |
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S_00B848_DX10_CLAMP(1) |
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S_00B848_FLOAT_MODE(variant->config.float_mode);
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S_00B848_FLOAT_MODE(variant->config.float_mode);
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variant->bo = device->ws->buffer_create(device->ws, binary.code_size, 256,
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variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
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RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS);
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RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS);
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void *ptr = device->ws->buffer_map(variant->bo);
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void *ptr = device->ws->buffer_map(variant->bo);
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memcpy(ptr, binary.code, binary.code_size);
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memcpy(ptr, binary->code, binary->code_size);
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device->ws->buffer_unmap(variant->bo);
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device->ws->buffer_unmap(variant->bo);
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}
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static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
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struct nir_shader *shader,
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struct radv_pipeline_layout *layout,
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const union ac_shader_variant_key *key,
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void** code_out,
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unsigned *code_size_out,
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bool dump)
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{
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struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
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enum radeon_family chip_family = device->instance->physicalDevice.rad_info.family;
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LLVMTargetMachineRef tm;
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if (!variant)
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return NULL;
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struct ac_nir_compiler_options options = {0};
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options.layout = layout;
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if (key)
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options.key = *key;
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struct ac_shader_binary binary;
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options.unsafe_math = env_var_as_boolean("RADV_UNSAFE_MATH", false);
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options.family = chip_family;
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options.chip_class = device->instance->physicalDevice.rad_info.chip_class;
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tm = ac_create_target_machine(chip_family);
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ac_compile_nir_shader(tm, &binary, &variant->config,
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&variant->info, shader, &options, dump);
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LLVMDisposeTargetMachine(tm);
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radv_fill_shader_variant(device, variant, &binary, shader->stage);
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if (code_out) {
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if (code_out) {
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*code_out = binary.code;
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*code_out = binary.code;
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*code_size_out = binary.code_size;
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*code_size_out = binary.code_size;
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