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radv/gfx10: Only set HW edge flags with gs & tess disabled.

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Reviewed-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Bas Nieuwenhuizen
2019-07-08 23:43:34 +02:00
committed by Dave Airlie
parent 9a8e4a07ad
commit 23c6698ea2
1 changed files with 2 additions and 1 deletions
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src/amd/vulkan/radv_pipeline.c
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@@ -3413,7 +3413,8 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
* flags in the shader.
*/
radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
S_028838_INDEX_BUF_EDGE_FLAG_ENA(1));
S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
!radv_pipeline_has_gs(pipeline)));
radeon_set_context_reg(ctx_cs, R_03096C_GE_CNTL,
S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |