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radeonsi: do not export VS outputs from vertex streams != 0

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This affects for GS copy shaders. When an output is meant for vertex
stream != 0, then we don't have to make it available to the pixel
shader.

There is a minor inefficiency here because the GLSL varying packing pass
does not group varyings of the same vertex stream together, but it
shouldn't be important in practice.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Nicolai Hähnle
2016-11-29 15:53:19 +01:00
parent fc0e009aa7
commit 21f2bb22a3
1 changed files with 6 additions and 0 deletions
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6
src/gallium/drivers/radeonsi/si_shader.c
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@@ -2394,6 +2394,12 @@ static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
break; break;
} }
if (outputs[i].vertex_stream[0] != 0 &&
outputs[i].vertex_stream[1] != 0 &&
outputs[i].vertex_stream[2] != 0 &&
outputs[i].vertex_stream[3] != 0)
export_param = false;
handle_semantic: handle_semantic:
/* Select the correct target */ /* Select the correct target */
switch(semantic_name) { switch(semantic_name) {