intel/compiler: emit actual barriers for working-group level barriers
Until now we have assumed that we could skip emitting these barriers in the general case based on empirical testing and a few assumptions detailed in a comment in the driver code, however, recent CTS tests have showed that we actually need them to produce correct behavior. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
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@@ -3926,6 +3926,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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break;
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}
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case nir_intrinsic_group_memory_barrier:
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case nir_intrinsic_memory_barrier_shared:
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case nir_intrinsic_memory_barrier_atomic_counter:
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case nir_intrinsic_memory_barrier_buffer:
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case nir_intrinsic_memory_barrier_image:
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@@ -3937,29 +3939,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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break;
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}
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case nir_intrinsic_group_memory_barrier:
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case nir_intrinsic_memory_barrier_shared:
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/* We treat these workgroup-level barriers as no-ops. This should be
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* safe at present and as long as:
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*
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* - Memory access instructions are not subsequently reordered by the
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* compiler back-end.
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*
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* - All threads from a given compute shader workgroup fit within a
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* single subslice and therefore talk to the same HDC shared unit
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* what supposedly guarantees ordering and coherency between threads
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* from the same workgroup. This may change in the future when we
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* start splitting workgroups across multiple subslices.
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*
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* - The context is not in fault-and-stream mode, which could cause
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* memory transactions (including to SLM) prior to the barrier to be
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* replayed after the barrier if a pagefault occurs. This shouldn't
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* be a problem up to and including SKL because fault-and-stream is
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* not usable due to hardware issues, but that's likely to change in
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* the future.
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*/
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break;
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case nir_intrinsic_shader_clock: {
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/* We cannot do anything if there is an event, so ignore it for now */
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const fs_reg shader_clock = get_timestamp(bld);
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