From 20ebdc3c2b0d083ce1de06209afe07ecb6c29a84 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 22 Aug 2022 19:08:12 +0200 Subject: [PATCH] radv: replace cs.uses_task_rings by ms.has_task MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Task shaders always use a ring, so this field was useless somehow. Signed-off-by: Samuel Pitoiset Reviewed-by: Timur Kristóf Part-of: --- src/amd/vulkan/radv_pipeline.c | 3 +-- src/amd/vulkan/radv_shader.h | 2 +- src/amd/vulkan/radv_shader_args.c | 8 ++++---- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 8d8673ca7d9..152d672cbd4 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3576,8 +3576,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, if (stages[MESA_SHADER_TASK].nir) { /* Task/mesh I/O uses the task ring buffers. */ - stages[MESA_SHADER_TASK].info.cs.uses_task_rings = true; - stages[MESA_SHADER_MESH].info.cs.uses_task_rings = true; + stages[MESA_SHADER_MESH].info.ms.has_task = true; stages[MESA_SHADER_TASK].info.workgroup_size = ac_compute_cs_workgroup_size( diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 81708b4615a..69a8df42719 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -349,7 +349,6 @@ struct radv_shader_info { bool uses_sbt; bool uses_ray_launch_size; - bool uses_task_rings; } cs; struct { uint64_t tes_inputs_read; @@ -365,6 +364,7 @@ struct radv_shader_info { struct radv_vs_output_info outinfo; enum shader_prim output_prim; bool needs_ms_scratch_ring; + bool has_task; /* If mesh shader is used together with a task shader. */ } ms; struct radv_streamout_info so; diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c index ae00a244efd..b04cca3e630 100644 --- a/src/amd/vulkan/radv_shader_args.c +++ b/src/amd/vulkan/radv_shader_args.c @@ -98,7 +98,7 @@ count_ms_user_sgprs(const struct radv_shader_info *info) if (info->vs.needs_draw_id) count++; - if (info->cs.uses_task_rings) + if (info->ms.has_task) count++; return count; @@ -179,7 +179,7 @@ allocate_user_sgprs(enum amd_gfx_level gfx_level, const struct radv_shader_info user_sgpr_count += 2; if (info->vs.needs_draw_id) user_sgpr_count += 1; - if (info->cs.uses_task_rings) + if (stage == MESA_SHADER_TASK) user_sgpr_count += 4; /* ring_entry, 2x ib_addr, ib_stride */ break; case MESA_SHADER_FRAGMENT: @@ -392,7 +392,7 @@ declare_ms_input_sgprs(const struct radv_shader_info *info, struct radv_shader_a if (info->vs.needs_draw_id) { ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.draw_id); } - if (info->cs.uses_task_rings) { + if (info->ms.has_task) { ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.task_ring_entry); } } @@ -592,7 +592,7 @@ radv_declare_shader_args(enum amd_gfx_level gfx_level, const struct radv_pipelin ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.draw_id); } - if (info->cs.uses_task_rings) { + if (stage == MESA_SHADER_TASK) { ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.task_ring_entry); ac_add_arg(&args->ac, AC_ARG_SGPR, 2, AC_ARG_INT, &args->task_ib_addr); ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->task_ib_stride);