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etnaviv: Use old set of state registers for PE configuration on GC880

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While the GC880 is HALTI0, it still uses the old set of state registers
for PE pipe configuration. This is another specialty of the GC880, readd
the missing handling for this GPU otherwise e.g. Qt5 cube example suffers
from rendering corruption with both eglfs and wayland backends.

Fixes: 7c46a48836 ("etnaviv: use new PE pipe address states on >= HALTI0")
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19562>
This commit is contained in:
Marek Vasut
2022-11-06 22:07:36 +01:00
committed by Marge Bot
parent 402a9a36f0
commit 20984aab0f
2 changed files with 4 additions and 4 deletions
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4
src/gallium/drivers/etnaviv/etnaviv_emit.c
View File

@@ -440,7 +440,7 @@ etna_emit_state(struct etna_context *ctx)
if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
/*0140C*/ EMIT_STATE(PE_DEPTH_NORMALIZE, ctx->framebuffer.PE_DEPTH_NORMALIZE);
if (screen->specs.halti < 0) {
if (screen->specs.halti < 0 || screen->model == 0x880) {
/*01410*/ EMIT_STATE_RELOC(PE_DEPTH_ADDR, &ctx->framebuffer.PE_DEPTH_ADDR);
}
@@ -477,7 +477,7 @@ etna_emit_state(struct etna_context *ctx)
/*0142C*/ EMIT_STATE(PE_COLOR_FORMAT, val);
}
if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
if (screen->specs.halti >= 0) {
if (screen->specs.halti >= 0 && screen->model != 0x880) {
/*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE);
/*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL);
/*01460*/ EMIT_STATE_RELOC(PE_PIPE_COLOR_ADDR(0), &ctx->framebuffer.PE_PIPE_COLOR_ADDR[0]);

4
src/gallium/drivers/etnaviv/etnaviv_state.c
View File

@@ -190,7 +190,7 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
cbuf->surf.offset, cbuf->surf.stride * 4);
}
if (screen->specs.halti >= 0) {
if (screen->specs.halti >= 0 && screen->model != 0x880) {
/* Rendertargets on GPUs with more than a single pixel pipe must always
* be multi-tiled, or single-buffer mode must be supported */
assert(screen->specs.pixel_pipes == 1 ||
@@ -273,7 +273,7 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
/* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
/* merged with depth_stencil_alpha */
if (screen->specs.halti >= 0) {
if (screen->specs.halti >= 0 && screen->model != 0x880) {
for (int i = 0; i < screen->specs.pixel_pipes; i++) {
cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;