anv: Implement VK_KHR_performance_query
This has the same kernel requirements are VK_INTEL_performance_query v2: Fix empty queue submit (Lionel) v3: Fix autotool build issue (Piotr Byszewski) v4: Fix Reset & Begin/End in same command buffer, using soft-pin & relocation on the same buffer won't work currently. This version uses a somewhat dirty trick in anv_execbuf_add_bo (Piotr Byszewski) v5: Fix enumeration with null pointers for either pCounters or pCounterDescriptions (Piotr) Fix return condition on enumeration (Lionel) Set counter uuid using sha1 hashes (Lionel) v6: Fix counters scope, should be COMMAND_KHR not COMMAND_BUFFER_KHR (Lionel) v7: Rebase (Lionel) v8: Rework checking for loaded queries (Lionel) v9: Use new i915-perf interface v10: Use anv_multialloc (Jason) v11: Implement perf query passes using self modifying batches (Lionel) Limit support to softpin/gen8 v12: Remove spurious changes (Jason) v13: Drop relocs (Jason) v14: Avoid overwritting .sType in VkPerformanceCounterKHR/VkPerformanceCounterDescriptionKHR (Lionel) v15: Don't copy the entire VkPerformanceCounterKHR/VkPerformanceCounterDescriptionKHR (Jason) Reuse anv_batch rather than custom packing (Jason) v16: Fix missing MI_BB_END in reconfiguration batch Only report the extension with kernel support (perf_version >= 3) v17: Some cleanup of unused stuff Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
This commit is contained in:
@@ -32,16 +32,32 @@
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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/* We reserve GPR 15 for conditional rendering */
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#define GEN_MI_BUILDER_NUM_ALLOC_GPRS 15
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/* We reserve :
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* - GPR 14 for perf queries
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* - GPR 15 for conditional rendering
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*/
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#define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
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#define GEN_MI_BUILDER_CAN_WRITE_BATCH GEN_GEN >= 8
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#define __gen_get_batch_dwords anv_batch_emit_dwords
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#define __gen_address_offset anv_address_add
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#define __gen_get_batch_address(b, a) anv_address_physical(anv_batch_address(b, a))
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#include "common/gen_mi_builder.h"
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#include "perf/gen_perf.h"
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#include "perf/gen_perf_mdapi.h"
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#define OA_REPORT_N_UINT64 (256 / sizeof(uint64_t))
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#include "vk_util.h"
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static struct anv_address
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anv_query_address(struct anv_query_pool *pool, uint32_t query)
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{
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return (struct anv_address) {
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.bo = pool->bo,
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.offset = query * pool->stride,
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};
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}
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VkResult genX(CreateQueryPool)(
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VkDevice _device,
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const VkQueryPoolCreateInfo* pCreateInfo,
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@@ -50,7 +66,11 @@ VkResult genX(CreateQueryPool)(
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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const struct anv_physical_device *pdevice = device->physical;
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const VkQueryPoolPerformanceCreateInfoKHR *perf_query_info = NULL;
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struct anv_query_pool *pool;
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struct gen_perf_counter_pass *counter_pass;
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struct gen_perf_query_info **pass_query;
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ANV_MULTIALLOC(ma);
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VkResult result;
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assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_QUERY_POOL_CREATE_INFO);
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@@ -65,17 +85,20 @@ VkResult genX(CreateQueryPool)(
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* 64bytes so we put those first and have the "available" bit behind
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* together with some other counters.
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*/
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uint32_t uint64s_per_slot = 1;
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uint32_t uint64s_per_slot = 0;
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UNUSED uint32_t n_passes = 0;
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anv_multialloc_add(&ma, &pool, 1);
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VkQueryPipelineStatisticFlags pipeline_statistics = 0;
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switch (pCreateInfo->queryType) {
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case VK_QUERY_TYPE_OCCLUSION:
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/* Occlusion queries have two values: begin and end. */
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uint64s_per_slot += 2;
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uint64s_per_slot = 1 + 2;
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break;
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case VK_QUERY_TYPE_TIMESTAMP:
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/* Timestamps just have the one timestamp value */
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uint64s_per_slot += 1;
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uint64s_per_slot = 1 + 1;
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break;
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case VK_QUERY_TYPE_PIPELINE_STATISTICS:
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pipeline_statistics = pCreateInfo->pipelineStatistics;
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@@ -85,25 +108,36 @@ VkResult genX(CreateQueryPool)(
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pipeline_statistics &= ANV_PIPELINE_STATISTICS_MASK;
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/* Statistics queries have a min and max for every statistic */
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uint64s_per_slot += 2 * util_bitcount(pipeline_statistics);
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uint64s_per_slot = 1 + 2 * util_bitcount(pipeline_statistics);
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break;
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case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:
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/* Transform feedback queries are 4 values, begin/end for
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* written/available.
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*/
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uint64s_per_slot += 4;
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uint64s_per_slot = 1 + 4;
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break;
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case VK_QUERY_TYPE_PERFORMANCE_QUERY_INTEL: {
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case VK_QUERY_TYPE_PERFORMANCE_QUERY_INTEL:
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uint64s_per_slot = 72; /* 576 bytes, see layout below */
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break;
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}
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case VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR:
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perf_query_info = vk_find_struct_const(pCreateInfo->pNext,
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QUERY_POOL_PERFORMANCE_CREATE_INFO_KHR);
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n_passes = gen_perf_get_n_passes(pdevice->perf,
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perf_query_info->pCounterIndices,
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perf_query_info->counterIndexCount,
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NULL);
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anv_multialloc_add(&ma, &counter_pass, perf_query_info->counterIndexCount);
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anv_multialloc_add(&ma, &pass_query, n_passes);
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STATIC_ASSERT(ANV_KHR_PERF_QUERY_SIZE % sizeof(uint64_t) == 0);
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uint64s_per_slot = (ANV_KHR_PERF_QUERY_SIZE / sizeof(uint64_t)) * n_passes;
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break;
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default:
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assert(!"Invalid query type");
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}
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pool = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8,
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VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
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if (pool == NULL)
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if (!anv_multialloc_alloc2(&ma, &device->vk.alloc,
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pAllocator,
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VK_SYSTEM_ALLOCATION_SCOPE_OBJECT))
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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vk_object_base_init(&device->vk, &pool->base, VK_OBJECT_TYPE_QUERY_POOL);
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@@ -112,6 +146,21 @@ VkResult genX(CreateQueryPool)(
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pool->stride = uint64s_per_slot * sizeof(uint64_t);
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pool->slots = pCreateInfo->queryCount;
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if (pool->type == VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR) {
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pool->n_counters = perf_query_info->counterIndexCount;
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pool->counter_pass = counter_pass;
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gen_perf_get_counters_passes(pdevice->perf,
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perf_query_info->pCounterIndices,
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perf_query_info->counterIndexCount,
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pool->counter_pass);
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pool->n_passes = n_passes;
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pool->pass_query = pass_query;
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gen_perf_get_n_passes(pdevice->perf,
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perf_query_info->pCounterIndices,
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perf_query_info->counterIndexCount,
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pool->pass_query);
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}
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uint32_t bo_flags = 0;
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if (pdevice->supports_48bit_addresses)
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bo_flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
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@@ -131,6 +180,23 @@ VkResult genX(CreateQueryPool)(
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if (result != VK_SUCCESS)
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goto fail;
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if (pool->type == VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR) {
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for (uint32_t p = 0; p < pool->n_passes; p++) {
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struct gen_mi_builder b;
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struct anv_batch batch = {
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.start = pool->bo->map + ANV_KHR_PERF_QUERY_SIZE * p + 8,
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.end = pool->bo->map + ANV_KHR_PERF_QUERY_SIZE * p + 64,
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};
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batch.next = batch.start;
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gen_mi_builder_init(&b, &batch);
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gen_mi_store(&b, gen_mi_reg64(ANV_PERF_QUERY_OFFSET_REG),
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gen_mi_imm(p * ANV_KHR_PERF_QUERY_SIZE));
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anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);
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assert(batch.next <= (pool->bo->map + ANV_KHR_PERF_QUERY_SIZE * p + 64));
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}
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}
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*pQueryPool = anv_query_pool_to_handle(pool);
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return VK_SUCCESS;
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@@ -157,15 +223,73 @@ void genX(DestroyQueryPool)(
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vk_free2(&device->vk.alloc, pAllocator, pool);
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}
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static struct anv_address
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anv_query_address(struct anv_query_pool *pool, uint32_t query)
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/**
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* VK_KHR_performance_query layout (576 bytes * number of passes) :
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*
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* -----------------------------------------
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* | availability (8b) | | |
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* |----------------------------| | |
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* | Small batch loading | | |
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* | ANV_PERF_QUERY_OFFSET_REG | | |
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* | (56b) | | Pass 0 |
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* |----------------------------| | |
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* | begin MI_RPC (256b) | | |
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* |----------------------------| | |
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* | end MI_RPC (256b) | | |
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* |----------------------------|-- | Query 0
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* | availability (8b) | | |
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* |----------------------------| | |
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* | Small batch loading | | |
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* | ANV_PERF_QUERY_OFFSET_REG | | |
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* | (56b) | | Pass 1 |
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* |----------------------------| | |
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* | begin MI_RPC (256b) | | |
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* |----------------------------| | |
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* | end MI_RPC (256b) | | |
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* |----------------------------|-----------
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* | availability (8b) | | |
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* |----------------------------| | |
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* | Unused (48b) | | |
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* |----------------------------| | Pass 0 |
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* | begin MI_RPC (256b) | | |
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* |----------------------------| | | Query 1
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* | end MI_RPC (256b) | | |
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* |----------------------------|-- |
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* | ... | | |
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* -----------------------------------------
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*/
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UNUSED static uint64_t
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khr_perf_query_availability_offset(struct anv_query_pool *pool, uint32_t query, uint32_t pass)
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{
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return (struct anv_address) {
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.bo = pool->bo,
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.offset = query * pool->stride,
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};
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return query * (pool->n_passes * ANV_KHR_PERF_QUERY_SIZE) +
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pass * ANV_KHR_PERF_QUERY_SIZE;
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}
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UNUSED static uint64_t
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khr_perf_query_oa_offset(struct anv_query_pool *pool, uint32_t query, uint32_t pass, bool end)
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{
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return query * (pool->n_passes * ANV_KHR_PERF_QUERY_SIZE) +
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pass * ANV_KHR_PERF_QUERY_SIZE +
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64 + (end ? OA_SNAPSHOT_SIZE : 0);
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}
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UNUSED static struct anv_address
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khr_perf_query_availability_address(struct anv_query_pool *pool, uint32_t query, uint32_t pass)
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{
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return anv_address_add(
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(struct anv_address) { .bo = pool->bo, },
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khr_perf_query_availability_offset(pool, query, pass));
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}
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UNUSED static struct anv_address
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khr_perf_query_oa_address(struct anv_query_pool *pool, uint32_t query, uint32_t pass, bool end)
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{
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return anv_address_add(
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(struct anv_address) { .bo = pool->bo, },
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khr_perf_query_oa_offset(pool, query, pass, end));
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}
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/**
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* VK_INTEL_performance_query layout (576 bytes) :
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*
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@@ -238,7 +362,17 @@ query_slot(struct anv_query_pool *pool, uint32_t query)
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static bool
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query_is_available(struct anv_query_pool *pool, uint32_t query)
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{
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return *(volatile uint64_t *)query_slot(pool, query);
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if (pool->type == VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR) {
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for (uint32_t p = 0; p < pool->n_passes; p++) {
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volatile uint64_t *slot =
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pool->bo->map + khr_perf_query_availability_offset(pool, query, p);
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if (!slot[0])
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return false;
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}
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return true;
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} else {
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return *(volatile uint64_t *)query_slot(pool, query);
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}
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}
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static VkResult
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@@ -275,6 +409,7 @@ VkResult genX(GetQueryPoolResults)(
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pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS ||
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pool->type == VK_QUERY_TYPE_TIMESTAMP ||
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pool->type == VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT ||
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pool->type == VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR ||
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pool->type == VK_QUERY_TYPE_PERFORMANCE_QUERY_INTEL);
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if (anv_device_is_lost(device))
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@@ -305,6 +440,12 @@ VkResult genX(GetQueryPoolResults)(
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* and vkGetQueryPoolResults returns VK_NOT_READY. However,
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* availability state is still written to pData for those queries if
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* VK_QUERY_RESULT_WITH_AVAILABILITY_BIT is set."
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*
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* From VK_KHR_performance_query :
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*
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* "VK_QUERY_RESULT_PERFORMANCE_QUERY_RECORDED_COUNTERS_BIT_KHR specifies
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* that the result should contain the number of counters that were recorded
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* into a query pool of type ename:VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR"
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*/
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bool write_results = available || (flags & VK_QUERY_RESULT_PARTIAL_BIT);
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@@ -367,6 +508,23 @@ VkResult genX(GetQueryPoolResults)(
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break;
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}
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#if GEN_GEN >= 8
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case VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR: {
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const struct anv_physical_device *pdevice = device->physical;
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assert((flags & (VK_QUERY_RESULT_WITH_AVAILABILITY_BIT |
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VK_QUERY_RESULT_PARTIAL_BIT)) == 0);
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for (uint32_t p = 0; p < pool->n_passes; p++) {
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const uint32_t *begin = pool->bo->map + khr_perf_query_oa_offset(pool, firstQuery + i, p, false);
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const uint32_t *end = pool->bo->map + khr_perf_query_oa_offset(pool, firstQuery + i, p, true);
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struct gen_perf_query_result result;
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gen_perf_query_result_clear(&result);
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gen_perf_query_result_accumulate(&result, pool->pass_query[p], begin, end);
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anv_perf_write_pass_results(pdevice->perf, pool, p, &result, pData);
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}
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break;
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}
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#endif
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case VK_QUERY_TYPE_PERFORMANCE_QUERY_INTEL: {
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if (!write_results)
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break;
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@@ -503,6 +661,23 @@ emit_zero_queries(struct anv_cmd_buffer *cmd_buffer,
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}
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break;
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#if GEN_GEN >= 8
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case VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR: {
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for (uint32_t i = 0; i < num_queries; i++) {
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for (uint32_t p = 0; p < pool->n_passes; p++) {
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gen_mi_memset(b,
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khr_perf_query_oa_address(pool,
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first_index + i, p, false),
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0, 2 * OA_SNAPSHOT_SIZE);
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emit_query_mi_availability(b,
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khr_perf_query_availability_address(pool, first_index + i, p),
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true);
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}
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}
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break;
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}
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#endif
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case VK_QUERY_TYPE_PERFORMANCE_QUERY_INTEL:
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for (uint32_t i = 0; i < num_queries; i++) {
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struct anv_address slot_addr =
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@@ -546,6 +721,23 @@ void genX(CmdResetQueryPool)(
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break;
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}
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#if GEN_GEN >= 8
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case VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR: {
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struct gen_mi_builder b;
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gen_mi_builder_init(&b, &cmd_buffer->batch);
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for (uint32_t i = 0; i < queryCount; i++) {
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for (uint32_t p = 0; p < pool->n_passes; p++) {
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emit_query_mi_availability(
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&b,
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khr_perf_query_availability_address(pool, firstQuery + i, p),
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false);
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}
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}
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break;
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}
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#endif
|
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case VK_QUERY_TYPE_PERFORMANCE_QUERY_INTEL: {
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struct gen_mi_builder b;
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gen_mi_builder_init(&b, &cmd_buffer->batch);
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@@ -569,8 +761,16 @@ void genX(ResetQueryPool)(
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ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
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for (uint32_t i = 0; i < queryCount; i++) {
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uint64_t *slot = query_slot(pool, firstQuery + i);
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*slot = 0;
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if (pool->type == VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR) {
|
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for (uint32_t p = 0; p < pool->n_passes; p++) {
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uint64_t *pass_slot = pool->bo->map +
|
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khr_perf_query_availability_offset(pool, firstQuery + i, p);
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*pass_slot = 0;
|
||||
}
|
||||
} else {
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||||
uint64_t *slot = query_slot(pool, firstQuery + i);
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*slot = 0;
|
||||
}
|
||||
}
|
||||
}
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||||
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@@ -665,6 +865,41 @@ void genX(CmdBeginQueryIndexedEXT)(
|
||||
emit_xfb_query(&b, index, anv_address_add(query_addr, 8));
|
||||
break;
|
||||
|
||||
#if GEN_GEN >= 8
|
||||
case VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR: {
|
||||
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
|
||||
pc.CommandStreamerStallEnable = true;
|
||||
pc.StallAtPixelScoreboard = true;
|
||||
}
|
||||
cmd_buffer->perf_query_pool = pool;
|
||||
|
||||
/* We know the bottom bits of the address are 0s which match what we
|
||||
* want in the MI_RPC packet.
|
||||
*/
|
||||
struct gen_mi_value mi_rpc_write_offset =
|
||||
gen_mi_iadd(
|
||||
&b,
|
||||
gen_mi_imm(
|
||||
gen_canonical_address(
|
||||
pool->bo->offset +
|
||||
khr_perf_query_oa_offset(pool, query, 0 /* pass */, false))),
|
||||
gen_mi_reg64(ANV_PERF_QUERY_OFFSET_REG));
|
||||
struct gen_mi_address_token mi_rpc_addr_dest =
|
||||
gen_mi_store_address(&b, mi_rpc_write_offset);
|
||||
gen_mi_self_mod_barrier(&b);
|
||||
|
||||
void *mi_rpc_dws =
|
||||
anv_batch_emitn(&cmd_buffer->batch,
|
||||
GENX(MI_REPORT_PERF_COUNT_length),
|
||||
GENX(MI_REPORT_PERF_COUNT),
|
||||
.MemoryAddress = query_addr /* Will be overwritten */ );
|
||||
_gen_mi_resolve_address_token(&b, mi_rpc_addr_dest,
|
||||
mi_rpc_dws +
|
||||
GENX(MI_REPORT_PERF_COUNT_MemoryAddress_start) / 8);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
case VK_QUERY_TYPE_PERFORMANCE_QUERY_INTEL: {
|
||||
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
|
||||
pc.CommandStreamerStallEnable = true;
|
||||
@@ -757,6 +992,60 @@ void genX(CmdEndQueryIndexedEXT)(
|
||||
emit_query_mi_availability(&b, query_addr, true);
|
||||
break;
|
||||
|
||||
#if GEN_GEN >= 8
|
||||
case VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR: {
|
||||
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
|
||||
pc.CommandStreamerStallEnable = true;
|
||||
pc.StallAtPixelScoreboard = true;
|
||||
}
|
||||
|
||||
/* We know the bottom bits of the address are 0s which match what we
|
||||
* want in the MI_RPC/MI_SDI packets.
|
||||
*/
|
||||
struct gen_mi_value mi_rpc_write_offset =
|
||||
gen_mi_iadd(
|
||||
&b,
|
||||
gen_mi_imm(
|
||||
gen_canonical_address(
|
||||
pool->bo->offset +
|
||||
khr_perf_query_oa_offset(pool, query, 0 /* pass*/, true))),
|
||||
gen_mi_reg64(ANV_PERF_QUERY_OFFSET_REG));
|
||||
struct gen_mi_value availability_write_offset =
|
||||
gen_mi_iadd(
|
||||
&b,
|
||||
gen_mi_imm(
|
||||
gen_canonical_address(
|
||||
pool->bo->offset +
|
||||
khr_perf_query_availability_offset(pool, query, 0 /* pass */))),
|
||||
gen_mi_reg64(ANV_PERF_QUERY_OFFSET_REG));
|
||||
|
||||
struct gen_mi_address_token mi_rpc_addr_dest =
|
||||
gen_mi_store_address(&b, mi_rpc_write_offset);
|
||||
struct gen_mi_address_token availability_addr_dest =
|
||||
gen_mi_store_address(&b, availability_write_offset);
|
||||
gen_mi_self_mod_barrier(&b);
|
||||
|
||||
void *mi_rpc_dws =
|
||||
anv_batch_emitn(&cmd_buffer->batch,
|
||||
GENX(MI_REPORT_PERF_COUNT_length),
|
||||
GENX(MI_REPORT_PERF_COUNT),
|
||||
.MemoryAddress = query_addr /* Will be overwritten */ );
|
||||
_gen_mi_resolve_address_token(&b, mi_rpc_addr_dest,
|
||||
mi_rpc_dws +
|
||||
GENX(MI_REPORT_PERF_COUNT_MemoryAddress_start) / 8);
|
||||
|
||||
void *availability_dws =
|
||||
anv_batch_emitn(&cmd_buffer->batch,
|
||||
GENX(MI_STORE_DATA_IMM_length),
|
||||
GENX(MI_STORE_DATA_IMM),
|
||||
.ImmediateData = true);
|
||||
_gen_mi_resolve_address_token(&b, availability_addr_dest,
|
||||
availability_dws +
|
||||
GENX(MI_STORE_DATA_IMM_Address_start) / 8);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
case VK_QUERY_TYPE_PERFORMANCE_QUERY_INTEL: {
|
||||
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
|
||||
pc.CommandStreamerStallEnable = true;
|
||||
@@ -1039,6 +1328,12 @@ void genX(CmdCopyQueryPoolResults)(
|
||||
gpu_write_query_result(&b, dest_addr, flags, 0, result);
|
||||
break;
|
||||
|
||||
#if GEN_GEN >= 8
|
||||
case VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR:
|
||||
unreachable("Copy KHR performance query results not implemented");
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
unreachable("unhandled query type");
|
||||
}
|
||||
|
Reference in New Issue
Block a user