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intel: Remove Gen10-specific cache config code

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Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6899>
This commit is contained in:
Ian Romanick
2020-09-24 13:02:41 -07:00
parent 9c19a3874d
commit 1f00b0f4ef
1 changed files with 0 additions and 20 deletions
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20
src/intel/common/gen_l3_config.c
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@@ -124,23 +124,6 @@ static const struct gen_l3_config bxt_2x6_l3_configs[] = {
}; };
DECLARE_L3_LIST(bxt_2x6); DECLARE_L3_LIST(bxt_2x6);
/**
* CNL validated L3 configurations. \sa ivb_l3_configs.
*/
static const struct gen_l3_config cnl_l3_configs[] = {
/* SLM URB ALL DC RO IS C T */
{{ 0, 64, 64, 0, 0, 0, 0, 0 }},
{{ 0, 64, 0, 16, 48, 0, 0, 0 }},
{{ 0, 48, 0, 16, 64, 0, 0, 0 }},
{{ 0, 32, 0, 0, 96, 0, 0, 0 }},
{{ 0, 32, 96, 0, 0, 0, 0, 0 }},
{{ 0, 32, 0, 16, 80, 0, 0, 0 }},
{{ 32, 16, 80, 0, 0, 0, 0, 0 }},
{{ 32, 16, 0, 64, 16, 0, 0, 0 }},
{{ 32, 0, 96, 0, 0, 0, 0, 0 }},
};
DECLARE_L3_LIST(cnl);
/** /**
* ICL validated L3 configurations. \sa icl_l3_configs. * ICL validated L3 configurations. \sa icl_l3_configs.
* Zeroth entry in below table has been commented out intentionally * Zeroth entry in below table has been commented out intentionally
@@ -192,9 +175,6 @@ get_l3_list(const struct gen_device_info *devinfo)
return &bxt_2x6_l3_list; return &bxt_2x6_l3_list;
return &chv_l3_list; return &chv_l3_list;
case 10:
return &cnl_l3_list;
case 11: case 11:
return &icl_l3_list; return &icl_l3_list;