From 1f00b0f4efac5438bb2c4896288e3b48b679fb1e Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Thu, 24 Sep 2020 13:02:41 -0700 Subject: [PATCH] intel: Remove Gen10-specific cache config code Reviewed-by: Jason Ekstrand Part-of: --- src/intel/common/gen_l3_config.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c index 347d7976226..db351712ab0 100644 --- a/src/intel/common/gen_l3_config.c +++ b/src/intel/common/gen_l3_config.c @@ -124,23 +124,6 @@ static const struct gen_l3_config bxt_2x6_l3_configs[] = { }; DECLARE_L3_LIST(bxt_2x6); -/** - * CNL validated L3 configurations. \sa ivb_l3_configs. - */ -static const struct gen_l3_config cnl_l3_configs[] = { - /* SLM URB ALL DC RO IS C T */ - {{ 0, 64, 64, 0, 0, 0, 0, 0 }}, - {{ 0, 64, 0, 16, 48, 0, 0, 0 }}, - {{ 0, 48, 0, 16, 64, 0, 0, 0 }}, - {{ 0, 32, 0, 0, 96, 0, 0, 0 }}, - {{ 0, 32, 96, 0, 0, 0, 0, 0 }}, - {{ 0, 32, 0, 16, 80, 0, 0, 0 }}, - {{ 32, 16, 80, 0, 0, 0, 0, 0 }}, - {{ 32, 16, 0, 64, 16, 0, 0, 0 }}, - {{ 32, 0, 96, 0, 0, 0, 0, 0 }}, -}; -DECLARE_L3_LIST(cnl); - /** * ICL validated L3 configurations. \sa icl_l3_configs. * Zeroth entry in below table has been commented out intentionally @@ -192,9 +175,6 @@ get_l3_list(const struct gen_device_info *devinfo) return &bxt_2x6_l3_list; return &chv_l3_list; - case 10: - return &cnl_l3_list; - case 11: return &icl_l3_list;