diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 12b28e32e80..1516060aa69 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -1180,7 +1180,7 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader
 
          config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) | S_00B12C_EXCP_EN(excp_en);
       } else {
-         bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
+         bool enable_prim_id = info->tes.outinfo.export_prim_id || info->uses_prim_id;
          vgpr_comp_cnt = enable_prim_id ? 3 : 2;
 
          config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
@@ -1231,7 +1231,7 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader
           */
          if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
             vgpr_comp_cnt = 3;
-         } else if (info->vs.export_prim_id) {
+         } else if (info->vs.outinfo.export_prim_id) {
             vgpr_comp_cnt = 2;
          } else if (info->vs.needs_instance_id) {
             vgpr_comp_cnt = 1;
@@ -1285,7 +1285,7 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader
       if (es_stage == MESA_SHADER_VERTEX) {
          es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
       } else if (es_stage == MESA_SHADER_TESS_EVAL) {
-         bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
+         bool enable_prim_id = info->tes.outinfo.export_prim_id || info->uses_prim_id;
          es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
       } else
          unreachable("Unexpected ES shader stage");
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 4055d709837..42076e553d4 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -307,7 +307,6 @@ struct radv_shader_info {
       struct radv_es_output_info es_info;
       bool as_es;
       bool as_ls;
-      bool export_prim_id;
       bool tcs_in_out_eq;
       uint64_t tcs_temp_only_input_mask;
       uint8_t num_linked_outputs;
@@ -338,7 +337,6 @@ struct radv_shader_info {
       enum gl_tess_spacing spacing;
       bool ccw;
       bool point_mode;
-      bool export_prim_id;
       uint8_t num_linked_inputs;
       uint8_t num_linked_patch_inputs;
       uint8_t num_linked_outputs;
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index 5f30a4b6153..d37c1e8fc37 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -664,7 +664,6 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n
       info->tes.ccw = nir->info.tess.ccw;
       info->tes.point_mode = nir->info.tess.point_mode;
       info->tes.as_es = key->vs_common_out.as_es;
-      info->tes.export_prim_id = key->vs_common_out.export_prim_id;
       info->is_ngg = key->vs_common_out.as_ngg;
       info->is_ngg_passthrough = key->vs_common_out.as_ngg_passthrough;
       break;
@@ -674,7 +673,6 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n
    case MESA_SHADER_VERTEX:
       info->vs.as_es = key->vs_common_out.as_es;
       info->vs.as_ls = key->vs_common_out.as_ls;
-      info->vs.export_prim_id = key->vs_common_out.export_prim_id;
       info->is_ngg = key->vs_common_out.as_ngg;
       info->is_ngg_passthrough = key->vs_common_out.as_ngg_passthrough;
       break;