intel/mi_builder: Drop the gen_ prefix
mi_ is already a unique prefix in Mesa so the gen_ isn't really gaining us anything except extra characters. It's possible that MI_ may conflict a tiny bit with GenXML but it doesn't seem to be a problem today and we can deal with that in the future if it's ever an issue. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9393>
This commit is contained in:
Jason Ekstrand
committed by
Marge Bot
Marge Bot
parent
6d522538b6
commit
1e53e0d2c7
@@ -39,7 +39,7 @@
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* - GPR 14 for secondary command buffer returns
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* - GPR 15 for conditional rendering
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*/
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#define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
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#define MI_BUILDER_NUM_ALLOC_GPRS 14
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#define __gen_get_batch_dwords anv_batch_emit_dwords
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#define __gen_address_offset anv_address_add
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#include "common/mi_builder.h"
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@@ -479,8 +479,8 @@ anv_image_init_aux_tt(struct anv_cmd_buffer *cmd_buffer,
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cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_END_OF_PIPE_SYNC_BIT;
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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struct gen_mi_builder b;
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gen_mi_builder_init(&b, &cmd_buffer->batch);
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struct mi_builder b;
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mi_builder_init(&b, &cmd_buffer->batch);
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for (uint32_t a = 0; a < layer_count; a++) {
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const uint32_t layer = base_layer + a;
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@@ -543,8 +543,7 @@ anv_image_init_aux_tt(struct anv_cmd_buffer *cmd_buffer,
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if (isl_aux_usage_has_ccs(image->planes[plane].aux_usage))
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new_aux_entry |= GEN_AUX_MAP_ENTRY_VALID_BIT;
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gen_mi_store(&b, gen_mi_mem64(aux_entry_address),
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gen_mi_imm(new_aux_entry));
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mi_store(&b, mi_mem64(aux_entry_address), mi_imm(new_aux_entry));
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}
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}
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@@ -778,12 +777,12 @@ anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
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enum isl_aux_op resolve_op,
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enum anv_fast_clear_type fast_clear_supported)
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{
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struct gen_mi_builder b;
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gen_mi_builder_init(&b, &cmd_buffer->batch);
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struct mi_builder b;
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mi_builder_init(&b, &cmd_buffer->batch);
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const struct gen_mi_value fast_clear_type =
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gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer->device,
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image, aspect));
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const struct mi_value fast_clear_type =
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mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer->device,
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image, aspect));
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if (resolve_op == ISL_AUX_OP_FULL_RESOLVE) {
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/* In this case, we're doing a full resolve which means we want the
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@@ -794,13 +793,12 @@ anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
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* if the first slice has been fast-cleared, it is also marked as
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* compressed. See also set_image_fast_clear_state.
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*/
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const struct gen_mi_value compression_state =
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gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer->device,
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image, aspect,
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level, array_layer));
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gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0),
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compression_state);
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gen_mi_store(&b, compression_state, gen_mi_imm(0));
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const struct mi_value compression_state =
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mi_mem32(anv_image_get_compression_state_addr(cmd_buffer->device,
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image, aspect,
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level, array_layer));
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mi_store(&b, mi_reg64(MI_PREDICATE_SRC0), compression_state);
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mi_store(&b, compression_state, mi_imm(0));
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if (level == 0 && array_layer == 0) {
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/* If the predicate is true, we want to write 0 to the fast clear type
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@@ -808,10 +806,10 @@ anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
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*
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* clear_type = clear_type & ~predicate;
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*/
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struct gen_mi_value new_fast_clear_type =
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gen_mi_iand(&b, fast_clear_type,
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gen_mi_inot(&b, gen_mi_reg64(MI_PREDICATE_SRC0)));
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gen_mi_store(&b, fast_clear_type, new_fast_clear_type);
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struct mi_value new_fast_clear_type =
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mi_iand(&b, fast_clear_type,
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mi_inot(&b, mi_reg64(MI_PREDICATE_SRC0)));
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mi_store(&b, fast_clear_type, new_fast_clear_type);
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}
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} else if (level == 0 && array_layer == 0) {
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/* In this case, we are doing a partial resolve to get rid of fast-clear
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@@ -822,19 +820,18 @@ anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
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assert(fast_clear_supported < ANV_FAST_CLEAR_ANY);
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/* We need to compute (fast_clear_supported < image->fast_clear) */
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struct gen_mi_value pred =
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gen_mi_ult(&b, gen_mi_imm(fast_clear_supported), fast_clear_type);
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gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0),
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gen_mi_value_ref(&b, pred));
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struct mi_value pred =
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mi_ult(&b, mi_imm(fast_clear_supported), fast_clear_type);
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mi_store(&b, mi_reg64(MI_PREDICATE_SRC0), mi_value_ref(&b, pred));
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/* If the predicate is true, we want to write 0 to the fast clear type
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* and, if it's false, leave it alone. We can do this by writing
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*
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* clear_type = clear_type & ~predicate;
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*/
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struct gen_mi_value new_fast_clear_type =
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gen_mi_iand(&b, fast_clear_type, gen_mi_inot(&b, pred));
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gen_mi_store(&b, fast_clear_type, new_fast_clear_type);
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struct mi_value new_fast_clear_type =
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mi_iand(&b, fast_clear_type, mi_inot(&b, pred));
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mi_store(&b, fast_clear_type, new_fast_clear_type);
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} else {
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/* In this case, we're trying to do a partial resolve on a slice that
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* doesn't have clear color. There's nothing to do.
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@@ -844,7 +841,7 @@ anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
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}
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/* Set src1 to 0 and use a != condition */
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gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0));
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mi_store(&b, mi_reg64(MI_PREDICATE_SRC1), mi_imm(0));
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anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
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mip.LoadOperation = LOAD_LOADINV;
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@@ -863,11 +860,11 @@ anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
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enum isl_aux_op resolve_op,
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enum anv_fast_clear_type fast_clear_supported)
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{
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struct gen_mi_builder b;
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gen_mi_builder_init(&b, &cmd_buffer->batch);
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struct mi_builder b;
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mi_builder_init(&b, &cmd_buffer->batch);
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struct gen_mi_value fast_clear_type_mem =
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gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer->device,
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struct mi_value fast_clear_type_mem =
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mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer->device,
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image, aspect));
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/* This only works for partial resolves and only when the clear color is
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@@ -885,9 +882,9 @@ anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
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* can't sample from CCS surfaces. It's enough to just load the fast clear
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* state into the predicate register.
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*/
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gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0), fast_clear_type_mem);
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gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0));
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gen_mi_store(&b, fast_clear_type_mem, gen_mi_imm(0));
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mi_store(&b, mi_reg64(MI_PREDICATE_SRC0), fast_clear_type_mem);
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mi_store(&b, mi_reg64(MI_PREDICATE_SRC1), mi_imm(0));
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mi_store(&b, fast_clear_type_mem, mi_imm(0));
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anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
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mip.LoadOperation = LOAD_LOADINV;
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@@ -1075,13 +1072,13 @@ genX(copy_fast_clear_dwords)(struct anv_cmd_buffer *cmd_buffer,
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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#endif
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struct gen_mi_builder b;
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gen_mi_builder_init(&b, &cmd_buffer->batch);
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struct mi_builder b;
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mi_builder_init(&b, &cmd_buffer->batch);
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if (copy_from_surface_state) {
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gen_mi_memcpy(&b, entry_addr, ss_clear_addr, copy_size);
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mi_memcpy(&b, entry_addr, ss_clear_addr, copy_size);
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} else {
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gen_mi_memcpy(&b, ss_clear_addr, entry_addr, copy_size);
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mi_memcpy(&b, ss_clear_addr, entry_addr, copy_size);
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/* Updating a surface state object may require that the state cache be
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* invalidated. From the SKL PRM, Shared Functions -> State -> State
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@@ -1820,10 +1817,10 @@ genX(CmdExecuteCommands)(
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* with conditional rendering, we should satisfy this dependency
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* regardless of conditional rendering being enabled in primary.
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*/
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struct gen_mi_builder b;
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gen_mi_builder_init(&b, &primary->batch);
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gen_mi_store(&b, gen_mi_reg64(ANV_PREDICATE_RESULT_REG),
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gen_mi_imm(UINT64_MAX));
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struct mi_builder b;
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mi_builder_init(&b, &primary->batch);
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mi_store(&b, mi_reg64(ANV_PREDICATE_RESULT_REG),
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mi_imm(UINT64_MAX));
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}
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}
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#endif
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@@ -3936,23 +3933,20 @@ void genX(CmdDrawIndirectByteCountEXT)(
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if (!pipeline->use_primitive_replication)
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instanceCount *= anv_subpass_view_count(cmd_buffer->state.subpass);
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struct gen_mi_builder b;
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gen_mi_builder_init(&b, &cmd_buffer->batch);
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struct gen_mi_value count =
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gen_mi_mem32(anv_address_add(counter_buffer->address,
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struct mi_builder b;
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mi_builder_init(&b, &cmd_buffer->batch);
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struct mi_value count =
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mi_mem32(anv_address_add(counter_buffer->address,
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counterBufferOffset));
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if (counterOffset)
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count = gen_mi_isub(&b, count, gen_mi_imm(counterOffset));
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count = gen_mi_udiv32_imm(&b, count, vertexStride);
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gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT), count);
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count = mi_isub(&b, count, mi_imm(counterOffset));
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count = mi_udiv32_imm(&b, count, vertexStride);
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mi_store(&b, mi_reg32(GEN7_3DPRIM_VERTEX_COUNT), count);
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gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX),
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gen_mi_imm(firstVertex));
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gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT),
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gen_mi_imm(instanceCount));
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gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE),
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gen_mi_imm(firstInstance));
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gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX), gen_mi_imm(0));
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mi_store(&b, mi_reg32(GEN7_3DPRIM_START_VERTEX), mi_imm(firstVertex));
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mi_store(&b, mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT), mi_imm(instanceCount));
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mi_store(&b, mi_reg32(GEN7_3DPRIM_START_INSTANCE), mi_imm(firstInstance));
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mi_store(&b, mi_reg32(GEN7_3DPRIM_BASE_VERTEX), mi_imm(0));
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anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
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prim.IndirectParameterEnable = true;
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@@ -3969,36 +3963,36 @@ load_indirect_parameters(struct anv_cmd_buffer *cmd_buffer,
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struct anv_address addr,
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bool indexed)
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{
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struct gen_mi_builder b;
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gen_mi_builder_init(&b, &cmd_buffer->batch);
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struct mi_builder b;
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mi_builder_init(&b, &cmd_buffer->batch);
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gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT),
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gen_mi_mem32(anv_address_add(addr, 0)));
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mi_store(&b, mi_reg32(GEN7_3DPRIM_VERTEX_COUNT),
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mi_mem32(anv_address_add(addr, 0)));
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struct gen_mi_value instance_count = gen_mi_mem32(anv_address_add(addr, 4));
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struct mi_value instance_count = mi_mem32(anv_address_add(addr, 4));
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unsigned view_count = anv_subpass_view_count(cmd_buffer->state.subpass);
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if (view_count > 1) {
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#if GEN_IS_HASWELL || GEN_GEN >= 8
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instance_count = gen_mi_imul_imm(&b, instance_count, view_count);
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instance_count = mi_imul_imm(&b, instance_count, view_count);
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#else
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anv_finishme("Multiview + indirect draw requires MI_MATH; "
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"MI_MATH is not supported on Ivy Bridge");
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#endif
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}
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gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT), instance_count);
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mi_store(&b, mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT), instance_count);
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gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX),
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gen_mi_mem32(anv_address_add(addr, 8)));
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mi_store(&b, mi_reg32(GEN7_3DPRIM_START_VERTEX),
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mi_mem32(anv_address_add(addr, 8)));
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if (indexed) {
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gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX),
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gen_mi_mem32(anv_address_add(addr, 12)));
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gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE),
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gen_mi_mem32(anv_address_add(addr, 16)));
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mi_store(&b, mi_reg32(GEN7_3DPRIM_BASE_VERTEX),
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mi_mem32(anv_address_add(addr, 12)));
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mi_store(&b, mi_reg32(GEN7_3DPRIM_START_INSTANCE),
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mi_mem32(anv_address_add(addr, 16)));
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} else {
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gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE),
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gen_mi_mem32(anv_address_add(addr, 12)));
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gen_mi_store(&b, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX), gen_mi_imm(0));
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mi_store(&b, mi_reg32(GEN7_3DPRIM_START_INSTANCE),
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mi_mem32(anv_address_add(addr, 12)));
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mi_store(&b, mi_reg32(GEN7_3DPRIM_BASE_VERTEX), mi_imm(0));
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}
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}
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@@ -4101,27 +4095,25 @@ void genX(CmdDrawIndexedIndirect)(
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}
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}
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static struct gen_mi_value
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static struct mi_value
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prepare_for_draw_count_predicate(struct anv_cmd_buffer *cmd_buffer,
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struct gen_mi_builder *b,
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struct mi_builder *b,
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struct anv_address count_address,
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const bool conditional_render_enabled)
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{
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struct gen_mi_value ret = gen_mi_imm(0);
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struct mi_value ret = mi_imm(0);
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if (conditional_render_enabled) {
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#if GEN_GEN >= 8 || GEN_IS_HASWELL
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ret = gen_mi_new_gpr(b);
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gen_mi_store(b, gen_mi_value_ref(b, ret), gen_mi_mem32(count_address));
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ret = mi_new_gpr(b);
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mi_store(b, mi_value_ref(b, ret), mi_mem32(count_address));
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#endif
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} else {
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/* Upload the current draw count from the draw parameters buffer to
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* MI_PREDICATE_SRC0.
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*/
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gen_mi_store(b, gen_mi_reg64(MI_PREDICATE_SRC0),
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gen_mi_mem32(count_address));
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gen_mi_store(b, gen_mi_reg32(MI_PREDICATE_SRC1 + 4), gen_mi_imm(0));
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mi_store(b, mi_reg64(MI_PREDICATE_SRC0), mi_mem32(count_address));
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mi_store(b, mi_reg32(MI_PREDICATE_SRC1 + 4), mi_imm(0));
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}
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return ret;
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@@ -4129,11 +4121,11 @@ prepare_for_draw_count_predicate(struct anv_cmd_buffer *cmd_buffer,
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static void
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emit_draw_count_predicate(struct anv_cmd_buffer *cmd_buffer,
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struct gen_mi_builder *b,
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struct mi_builder *b,
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uint32_t draw_index)
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{
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/* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
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gen_mi_store(b, gen_mi_reg32(MI_PREDICATE_SRC1), gen_mi_imm(draw_index));
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mi_store(b, mi_reg32(MI_PREDICATE_SRC1), mi_imm(draw_index));
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if (draw_index == 0) {
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anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
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@@ -4161,22 +4153,22 @@ emit_draw_count_predicate(struct anv_cmd_buffer *cmd_buffer,
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static void
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emit_draw_count_predicate_with_conditional_render(
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struct anv_cmd_buffer *cmd_buffer,
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struct gen_mi_builder *b,
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struct mi_builder *b,
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uint32_t draw_index,
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struct gen_mi_value max)
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struct mi_value max)
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{
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struct gen_mi_value pred = gen_mi_ult(b, gen_mi_imm(draw_index), max);
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pred = gen_mi_iand(b, pred, gen_mi_reg64(ANV_PREDICATE_RESULT_REG));
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struct mi_value pred = mi_ult(b, mi_imm(draw_index), max);
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pred = mi_iand(b, pred, mi_reg64(ANV_PREDICATE_RESULT_REG));
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#if GEN_GEN >= 8
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gen_mi_store(b, gen_mi_reg64(MI_PREDICATE_RESULT), pred);
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mi_store(b, mi_reg64(MI_PREDICATE_RESULT), pred);
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#else
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/* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
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* so we emit MI_PREDICATE to set it.
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*/
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gen_mi_store(b, gen_mi_reg64(MI_PREDICATE_SRC0), pred);
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gen_mi_store(b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0));
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mi_store(b, mi_reg64(MI_PREDICATE_SRC0), pred);
|
||||
mi_store(b, mi_reg64(MI_PREDICATE_SRC1), mi_imm(0));
|
||||
|
||||
anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
|
||||
mip.LoadOperation = LOAD_LOADINV;
|
||||
@@ -4208,11 +4200,11 @@ void genX(CmdDrawIndirectCount)(
|
||||
|
||||
genX(cmd_buffer_flush_state)(cmd_buffer);
|
||||
|
||||
struct gen_mi_builder b;
|
||||
gen_mi_builder_init(&b, &cmd_buffer->batch);
|
||||
struct mi_builder b;
|
||||
mi_builder_init(&b, &cmd_buffer->batch);
|
||||
struct anv_address count_address =
|
||||
anv_address_add(count_buffer->address, countBufferOffset);
|
||||
struct gen_mi_value max =
|
||||
struct mi_value max =
|
||||
prepare_for_draw_count_predicate(cmd_buffer, &b, count_address,
|
||||
cmd_state->conditional_render_enabled);
|
||||
|
||||
@@ -4222,7 +4214,7 @@ void genX(CmdDrawIndirectCount)(
|
||||
#if GEN_GEN >= 8 || GEN_IS_HASWELL
|
||||
if (cmd_state->conditional_render_enabled) {
|
||||
emit_draw_count_predicate_with_conditional_render(
|
||||
cmd_buffer, &b, i, gen_mi_value_ref(&b, max));
|
||||
cmd_buffer, &b, i, mi_value_ref(&b, max));
|
||||
} else {
|
||||
emit_draw_count_predicate(cmd_buffer, &b, i);
|
||||
}
|
||||
@@ -4255,7 +4247,7 @@ void genX(CmdDrawIndirectCount)(
|
||||
offset += stride;
|
||||
}
|
||||
|
||||
gen_mi_value_unref(&b, max);
|
||||
mi_value_unref(&b, max);
|
||||
}
|
||||
|
||||
void genX(CmdDrawIndexedIndirectCount)(
|
||||
@@ -4279,11 +4271,11 @@ void genX(CmdDrawIndexedIndirectCount)(
|
||||
|
||||
genX(cmd_buffer_flush_state)(cmd_buffer);
|
||||
|
||||
struct gen_mi_builder b;
|
||||
gen_mi_builder_init(&b, &cmd_buffer->batch);
|
||||
struct mi_builder b;
|
||||
mi_builder_init(&b, &cmd_buffer->batch);
|
||||
struct anv_address count_address =
|
||||
anv_address_add(count_buffer->address, countBufferOffset);
|
||||
struct gen_mi_value max =
|
||||
struct mi_value max =
|
||||
prepare_for_draw_count_predicate(cmd_buffer, &b, count_address,
|
||||
cmd_state->conditional_render_enabled);
|
||||
|
||||
@@ -4293,7 +4285,7 @@ void genX(CmdDrawIndexedIndirectCount)(
|
||||
#if GEN_GEN >= 8 || GEN_IS_HASWELL
|
||||
if (cmd_state->conditional_render_enabled) {
|
||||
emit_draw_count_predicate_with_conditional_render(
|
||||
cmd_buffer, &b, i, gen_mi_value_ref(&b, max));
|
||||
cmd_buffer, &b, i, mi_value_ref(&b, max));
|
||||
} else {
|
||||
emit_draw_count_predicate(cmd_buffer, &b, i);
|
||||
}
|
||||
@@ -4327,7 +4319,7 @@ void genX(CmdDrawIndexedIndirectCount)(
|
||||
offset += stride;
|
||||
}
|
||||
|
||||
gen_mi_value_unref(&b, max);
|
||||
mi_value_unref(&b, max);
|
||||
}
|
||||
|
||||
void genX(CmdBeginTransformFeedbackEXT)(
|
||||
@@ -4755,21 +4747,21 @@ void genX(CmdDispatchIndirect)(
|
||||
|
||||
genX(cmd_buffer_flush_compute_state)(cmd_buffer);
|
||||
|
||||
struct gen_mi_builder b;
|
||||
gen_mi_builder_init(&b, &cmd_buffer->batch);
|
||||
struct mi_builder b;
|
||||
mi_builder_init(&b, &cmd_buffer->batch);
|
||||
|
||||
struct gen_mi_value size_x = gen_mi_mem32(anv_address_add(addr, 0));
|
||||
struct gen_mi_value size_y = gen_mi_mem32(anv_address_add(addr, 4));
|
||||
struct gen_mi_value size_z = gen_mi_mem32(anv_address_add(addr, 8));
|
||||
struct mi_value size_x = mi_mem32(anv_address_add(addr, 0));
|
||||
struct mi_value size_y = mi_mem32(anv_address_add(addr, 4));
|
||||
struct mi_value size_z = mi_mem32(anv_address_add(addr, 8));
|
||||
|
||||
gen_mi_store(&b, gen_mi_reg32(GPGPU_DISPATCHDIMX), size_x);
|
||||
gen_mi_store(&b, gen_mi_reg32(GPGPU_DISPATCHDIMY), size_y);
|
||||
gen_mi_store(&b, gen_mi_reg32(GPGPU_DISPATCHDIMZ), size_z);
|
||||
mi_store(&b, mi_reg32(GPGPU_DISPATCHDIMX), size_x);
|
||||
mi_store(&b, mi_reg32(GPGPU_DISPATCHDIMY), size_y);
|
||||
mi_store(&b, mi_reg32(GPGPU_DISPATCHDIMZ), size_z);
|
||||
|
||||
#if GEN_GEN <= 7
|
||||
/* predicate = (compute_dispatch_indirect_x_size == 0); */
|
||||
gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0), size_x);
|
||||
gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0));
|
||||
mi_store(&b, mi_reg64(MI_PREDICATE_SRC0), size_x);
|
||||
mi_store(&b, mi_reg64(MI_PREDICATE_SRC1), mi_imm(0));
|
||||
anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
|
||||
mip.LoadOperation = LOAD_LOAD;
|
||||
mip.CombineOperation = COMBINE_SET;
|
||||
@@ -4777,7 +4769,7 @@ void genX(CmdDispatchIndirect)(
|
||||
}
|
||||
|
||||
/* predicate |= (compute_dispatch_indirect_y_size == 0); */
|
||||
gen_mi_store(&b, gen_mi_reg32(MI_PREDICATE_SRC0), size_y);
|
||||
mi_store(&b, mi_reg32(MI_PREDICATE_SRC0), size_y);
|
||||
anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
|
||||
mip.LoadOperation = LOAD_LOAD;
|
||||
mip.CombineOperation = COMBINE_OR;
|
||||
@@ -4785,7 +4777,7 @@ void genX(CmdDispatchIndirect)(
|
||||
}
|
||||
|
||||
/* predicate |= (compute_dispatch_indirect_z_size == 0); */
|
||||
gen_mi_store(&b, gen_mi_reg32(MI_PREDICATE_SRC0), size_z);
|
||||
mi_store(&b, mi_reg32(MI_PREDICATE_SRC0), size_z);
|
||||
anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
|
||||
mip.LoadOperation = LOAD_LOAD;
|
||||
mip.CombineOperation = COMBINE_OR;
|
||||
@@ -4802,8 +4794,8 @@ void genX(CmdDispatchIndirect)(
|
||||
#if GEN_IS_HASWELL
|
||||
if (cmd_buffer->state.conditional_render_enabled) {
|
||||
/* predicate &= !(conditional_rendering_predicate == 0); */
|
||||
gen_mi_store(&b, gen_mi_reg32(MI_PREDICATE_SRC0),
|
||||
gen_mi_reg32(ANV_PREDICATE_RESULT_REG));
|
||||
mi_store(&b, mi_reg32(MI_PREDICATE_SRC0),
|
||||
mi_reg32(ANV_PREDICATE_RESULT_REG));
|
||||
anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
|
||||
mip.LoadOperation = LOAD_LOADINV;
|
||||
mip.CombineOperation = COMBINE_AND;
|
||||
@@ -6198,12 +6190,12 @@ void
|
||||
genX(cmd_emit_conditional_render_predicate)(struct anv_cmd_buffer *cmd_buffer)
|
||||
{
|
||||
#if GEN_GEN >= 8 || GEN_IS_HASWELL
|
||||
struct gen_mi_builder b;
|
||||
gen_mi_builder_init(&b, &cmd_buffer->batch);
|
||||
struct mi_builder b;
|
||||
mi_builder_init(&b, &cmd_buffer->batch);
|
||||
|
||||
gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0),
|
||||
gen_mi_reg32(ANV_PREDICATE_RESULT_REG));
|
||||
gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0));
|
||||
mi_store(&b, mi_reg64(MI_PREDICATE_SRC0),
|
||||
mi_reg32(ANV_PREDICATE_RESULT_REG));
|
||||
mi_store(&b, mi_reg64(MI_PREDICATE_SRC1), mi_imm(0));
|
||||
|
||||
anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
|
||||
mip.LoadOperation = LOAD_LOADINV;
|
||||
@@ -6231,8 +6223,8 @@ void genX(CmdBeginConditionalRenderingEXT)(
|
||||
|
||||
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
|
||||
|
||||
struct gen_mi_builder b;
|
||||
gen_mi_builder_init(&b, &cmd_buffer->batch);
|
||||
struct mi_builder b;
|
||||
mi_builder_init(&b, &cmd_buffer->batch);
|
||||
|
||||
/* Section 19.4 of the Vulkan 1.1.85 spec says:
|
||||
*
|
||||
@@ -6245,15 +6237,15 @@ void genX(CmdBeginConditionalRenderingEXT)(
|
||||
*
|
||||
* So it's perfectly fine to read a value from the buffer once.
|
||||
*/
|
||||
struct gen_mi_value value = gen_mi_mem32(value_address);
|
||||
struct mi_value value = mi_mem32(value_address);
|
||||
|
||||
/* Precompute predicate result, it is necessary to support secondary
|
||||
* command buffers since it is unknown if conditional rendering is
|
||||
* inverted when populating them.
|
||||
*/
|
||||
gen_mi_store(&b, gen_mi_reg64(ANV_PREDICATE_RESULT_REG),
|
||||
isInverted ? gen_mi_uge(&b, gen_mi_imm(0), value) :
|
||||
gen_mi_ult(&b, gen_mi_imm(0), value));
|
||||
mi_store(&b, mi_reg64(ANV_PREDICATE_RESULT_REG),
|
||||
isInverted ? mi_uge(&b, mi_imm(0), value) :
|
||||
mi_ult(&b, mi_imm(0), value));
|
||||
}
|
||||
|
||||
void genX(CmdEndConditionalRenderingEXT)(
|
||||
|
||||
Reference in New Issue
Block a user