aco: Format.

Manually adjusted some comments for more intuitive line breaks. Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11258>
2021-06-09 10:14:54 +02:00
parent 97ec360dc4
commit 1e2639026f
32 changed files with 7231 additions and 6574 deletions
--- a/src/amd/compiler/aco_ir.cpp
+++ b/src/amd/compiler/aco_ir.cpp
@@ -32,39 +32,40 @@ namespace aco {

 uint64_t debug_flags = 0;

-static const struct debug_control aco_debug_options[] = {
-   {"validateir", DEBUG_VALIDATE_IR},
-   {"validatera", DEBUG_VALIDATE_RA},
-   {"perfwarn", DEBUG_PERFWARN},
-   {"force-waitcnt", DEBUG_FORCE_WAITCNT},
-   {"novn", DEBUG_NO_VN},
-   {"noopt", DEBUG_NO_OPT},
-   {"nosched", DEBUG_NO_SCHED},
-   {"perfinfo", DEBUG_PERF_INFO},
-   {"liveinfo", DEBUG_LIVE_INFO},
-   {NULL, 0}
-};
+static const struct debug_control aco_debug_options[] = {{"validateir", DEBUG_VALIDATE_IR},
+                                                         {"validatera", DEBUG_VALIDATE_RA},
+                                                         {"perfwarn", DEBUG_PERFWARN},
+                                                         {"force-waitcnt", DEBUG_FORCE_WAITCNT},
+                                                         {"novn", DEBUG_NO_VN},
+                                                         {"noopt", DEBUG_NO_OPT},
+                                                         {"nosched", DEBUG_NO_SCHED},
+                                                         {"perfinfo", DEBUG_PERF_INFO},
+                                                         {"liveinfo", DEBUG_LIVE_INFO},
+                                                         {NULL, 0}};

 static once_flag init_once_flag = ONCE_FLAG_INIT;

-static void init_once()
+static void
+init_once()
 {
   debug_flags = parse_debug_string(getenv("ACO_DEBUG"), aco_debug_options);

-   #ifndef NDEBUG
+#ifndef NDEBUG
   /* enable some flags by default on debug builds */
   debug_flags |= aco::DEBUG_VALIDATE_IR;
-   #endif
+#endif
 }

-void init()
+void
+init()
 {
   call_once(&init_once_flag, init_once);
 }

-void init_program(Program *program, Stage stage, struct radv_shader_info *info,
-                  enum chip_class chip_class, enum radeon_family family,
-                  bool wgp_mode, ac_shader_config *config)
+void
+init_program(Program* program, Stage stage, struct radv_shader_info* info,
+             enum chip_class chip_class, enum radeon_family family, bool wgp_mode,
+             ac_shader_config* config)
 {
   program->stage = stage;
   program->config = config;
@@ -72,24 +73,12 @@ void init_program(Program *program, Stage stage, struct radv_shader_info *info,
   program->chip_class = chip_class;
   if (family == CHIP_UNKNOWN) {
      switch (chip_class) {
-      case GFX6:
-         program->family = CHIP_TAHITI;
-         break;
-      case GFX7:
-         program->family = CHIP_BONAIRE;
-         break;
-      case GFX8:
-         program->family = CHIP_POLARIS10;
-         break;
-      case GFX9:
-         program->family = CHIP_VEGA10;
-         break;
-      case GFX10:
-         program->family = CHIP_NAVI10;
-         break;
-      default:
-         program->family = CHIP_UNKNOWN;
-         break;
+      case GFX6: program->family = CHIP_TAHITI; break;
+      case GFX7: program->family = CHIP_BONAIRE; break;
+      case GFX8: program->family = CHIP_POLARIS10; break;
+      case GFX9: program->family = CHIP_VEGA10; break;
+      case GFX10: program->family = CHIP_NAVI10; break;
+      default: program->family = CHIP_UNKNOWN; break;
      }
   } else {
      program->family = family;
@@ -98,7 +87,8 @@ void init_program(Program *program, Stage stage, struct radv_shader_info *info,
   program->lane_mask = program->wave_size == 32 ? s1 : s2;

   program->dev.lds_encoding_granule = chip_class >= GFX7 ? 512 : 256;
-   program->dev.lds_alloc_granule = chip_class >= GFX10_3 ? 1024 : program->dev.lds_encoding_granule;
+   program->dev.lds_alloc_granule =
+      chip_class >= GFX10_3 ? 1024 : program->dev.lds_encoding_granule;
   program->dev.lds_limit = chip_class >= GFX7 ? 65536 : 32768;
   /* apparently gfx702 also has 16-bank LDS but I can't find a family for that */
   program->dev.has_16bank_lds = family == CHIP_KABINI || family == CHIP_STONEY;
@@ -111,7 +101,8 @@ void init_program(Program *program, Stage stage, struct radv_shader_info *info,
      program->dev.physical_sgprs = 5120; /* doesn't matter as long as it's at least 128 * 40 */
      program->dev.physical_vgprs = program->wave_size == 32 ? 1024 : 512;
      program->dev.sgpr_alloc_granule = 128;
-      program->dev.sgpr_limit = 108; /* includes VCC, which can be treated as s[106-107] on GFX10+ */
+      program->dev.sgpr_limit =
+         108; /* includes VCC, which can be treated as s[106-107] on GFX10+ */
      if (chip_class >= GFX10_3)
         program->dev.vgpr_alloc_granule = program->wave_size == 32 ? 16 : 8;
      else
@@ -145,18 +136,14 @@ void init_program(Program *program, Stage stage, struct radv_shader_info *info,
   /* GFX9 APUS */
   case CHIP_RAVEN:
   case CHIP_RAVEN2:
-   case CHIP_RENOIR:
-      program->dev.xnack_enabled = true;
-      break;
-   default:
-      break;
+   case CHIP_RENOIR: program->dev.xnack_enabled = true; break;
+   default: break;
   }

   program->dev.sram_ecc_enabled = program->family == CHIP_ARCTURUS;
   /* apparently gfx702 also has fast v_fma_f32 but I can't find a family for that */
   program->dev.has_fast_fma32 = program->chip_class >= GFX9;
-   if (program->family == CHIP_TAHITI ||
-       program->family == CHIP_CARRIZO ||
+   if (program->family == CHIP_TAHITI || program->family == CHIP_CARRIZO ||
       program->family == CHIP_HAWAII)
      program->dev.has_fast_fma32 = true;

@@ -176,29 +163,24 @@ void init_program(Program *program, Stage stage, struct radv_shader_info *info,
   program->next_fp_mode.round32 = fp_round_ne;
 }

-memory_sync_info get_sync_info(const Instruction* instr)
+memory_sync_info
+get_sync_info(const Instruction* instr)
 {
   switch (instr->format) {
-   case Format::SMEM:
-      return instr->smem().sync;
-   case Format::MUBUF:
-      return instr->mubuf().sync;
-   case Format::MIMG:
-      return instr->mimg().sync;
-   case Format::MTBUF:
-      return instr->mtbuf().sync;
+   case Format::SMEM: return instr->smem().sync;
+   case Format::MUBUF: return instr->mubuf().sync;
+   case Format::MIMG: return instr->mimg().sync;
+   case Format::MTBUF: return instr->mtbuf().sync;
   case Format::FLAT:
   case Format::GLOBAL:
-   case Format::SCRATCH:
-      return instr->flatlike().sync;
-   case Format::DS:
-      return instr->ds().sync;
-   default:
-      return memory_sync_info();
+   case Format::SCRATCH: return instr->flatlike().sync;
+   case Format::DS: return instr->ds().sync;
+   default: return memory_sync_info();
   }
 }

-bool can_use_SDWA(chip_class chip, const aco_ptr<Instruction>& instr, bool pre_ra)
+bool
+can_use_SDWA(chip_class chip, const aco_ptr<Instruction>& instr, bool pre_ra)
 {
   if (!instr->isVALU())
      return false;
@@ -218,7 +200,7 @@ bool can_use_SDWA(chip_class chip, const aco_ptr<Instruction>& instr, bool pre_r
      if (vop3.omod && chip < GFX9)
         return false;

-      //TODO: return true if we know we will use vcc
+      // TODO: return true if we know we will use vcc
      if (!pre_ra && instr->definitions.size() >= 2)
         return false;

@@ -244,38 +226,36 @@ bool can_use_SDWA(chip_class chip, const aco_ptr<Instruction>& instr, bool pre_r
         return false;
   }

-   bool is_mac = instr->opcode == aco_opcode::v_mac_f32 ||
-                 instr->opcode == aco_opcode::v_mac_f16 ||
-                 instr->opcode == aco_opcode::v_fmac_f32 ||
-                 instr->opcode == aco_opcode::v_fmac_f16;
+   bool is_mac = instr->opcode == aco_opcode::v_mac_f32 || instr->opcode == aco_opcode::v_mac_f16 ||
+                 instr->opcode == aco_opcode::v_fmac_f32 || instr->opcode == aco_opcode::v_fmac_f16;

   if (chip != GFX8 && is_mac)
      return false;

-   //TODO: return true if we know we will use vcc
+   // TODO: return true if we know we will use vcc
   if (!pre_ra && instr->isVOPC())
      return false;
   if (!pre_ra && instr->operands.size() >= 3 && !is_mac)
      return false;

-   return instr->opcode != aco_opcode::v_madmk_f32 &&
-          instr->opcode != aco_opcode::v_madak_f32 &&
-          instr->opcode != aco_opcode::v_madmk_f16 &&
-          instr->opcode != aco_opcode::v_madak_f16 &&
+   return instr->opcode != aco_opcode::v_madmk_f32 && instr->opcode != aco_opcode::v_madak_f32 &&
+          instr->opcode != aco_opcode::v_madmk_f16 && instr->opcode != aco_opcode::v_madak_f16 &&
          instr->opcode != aco_opcode::v_readfirstlane_b32 &&
-          instr->opcode != aco_opcode::v_clrexcp &&
-          instr->opcode != aco_opcode::v_swap_b32;
+          instr->opcode != aco_opcode::v_clrexcp && instr->opcode != aco_opcode::v_swap_b32;
 }

 /* updates "instr" and returns the old instruction (or NULL if no update was needed) */
-aco_ptr<Instruction> convert_to_SDWA(chip_class chip, aco_ptr<Instruction>& instr)
+aco_ptr<Instruction>
+convert_to_SDWA(chip_class chip, aco_ptr<Instruction>& instr)
 {
   if (instr->isSDWA())
      return NULL;

   aco_ptr<Instruction> tmp = std::move(instr);
-   Format format = (Format)(((uint16_t)tmp->format & ~(uint16_t)Format::VOP3) | (uint16_t)Format::SDWA);
-   instr.reset(create_instruction<SDWA_instruction>(tmp->opcode, format, tmp->operands.size(), tmp->definitions.size()));
+   Format format =
+      (Format)(((uint16_t)tmp->format & ~(uint16_t)Format::VOP3) | (uint16_t)Format::SDWA);
+   instr.reset(create_instruction<SDWA_instruction>(tmp->opcode, format, tmp->operands.size(),
+                                                    tmp->definitions.size()));
   std::copy(tmp->operands.cbegin(), tmp->operands.cend(), instr->operands.begin());
   std::copy(tmp->definitions.cbegin(), tmp->definitions.cend(), instr->definitions.begin());

@@ -295,15 +275,9 @@ aco_ptr<Instruction> convert_to_SDWA(chip_class chip, aco_ptr<Instruction>& inst
         break;

      switch (instr->operands[i].bytes()) {
-      case 1:
-         sdwa.sel[i] = sdwa_ubyte;
-         break;
-      case 2:
-         sdwa.sel[i] = sdwa_uword;
-         break;
-      case 4:
-         sdwa.sel[i] = sdwa_udword;
-         break;
+      case 1: sdwa.sel[i] = sdwa_ubyte; break;
+      case 2: sdwa.sel[i] = sdwa_uword; break;
+      case 4: sdwa.sel[i] = sdwa_udword; break;
      }
   }
   switch (instr->definitions[0].bytes()) {
@@ -315,9 +289,7 @@ aco_ptr<Instruction> convert_to_SDWA(chip_class chip, aco_ptr<Instruction>& inst
      sdwa.dst_sel = sdwa_uword;
      sdwa.dst_preserve = true;
      break;
-   case 4:
-      sdwa.dst_sel = sdwa_udword;
-      break;
+   case 4: sdwa.dst_sel = sdwa_udword; break;
   }

   if (instr->definitions[0].getTemp().type() == RegType::sgpr && chip == GFX8)
@@ -330,7 +302,8 @@ aco_ptr<Instruction> convert_to_SDWA(chip_class chip, aco_ptr<Instruction>& inst
   return tmp;
 }

-bool can_use_opsel(chip_class chip, aco_opcode op, int idx, bool high)
+bool
+can_use_opsel(chip_class chip, aco_opcode op, int idx, bool high)
 {
   /* opsel is only GFX9+ */
   if ((high || idx == -1) && chip < GFX9)
@@ -362,21 +335,18 @@ bool can_use_opsel(chip_class chip, aco_opcode op, int idx, bool high)
   case aco_opcode::v_lshlrev_b16_e64:
   case aco_opcode::v_lshrrev_b16_e64:
   case aco_opcode::v_ashrrev_i16_e64:
-   case aco_opcode::v_mul_lo_u16_e64:
-      return true;
+   case aco_opcode::v_mul_lo_u16_e64: return true;
   case aco_opcode::v_pack_b32_f16:
   case aco_opcode::v_cvt_pknorm_i16_f16:
-   case aco_opcode::v_cvt_pknorm_u16_f16:
-      return idx != -1;
+   case aco_opcode::v_cvt_pknorm_u16_f16: return idx != -1;
   case aco_opcode::v_mad_u32_u16:
-   case aco_opcode::v_mad_i32_i16:
-      return idx >= 0 && idx < 2;
-   default:
-      return false;
+   case aco_opcode::v_mad_i32_i16: return idx >= 0 && idx < 2;
+   default: return false;
   }
 }

-uint32_t get_reduction_identity(ReduceOp op, unsigned idx)
+uint32_t
+get_reduction_identity(ReduceOp op, unsigned idx)
 {
   switch (op) {
   case iadd8:
@@ -397,65 +367,44 @@ uint32_t get_reduction_identity(ReduceOp op, unsigned idx)
   case umax8:
   case umax16:
   case umax32:
-   case umax64:
-      return 0;
+   case umax64: return 0;
   case imul8:
   case imul16:
   case imul32:
-   case imul64:
-      return idx ? 0 : 1;
-   case fmul16:
-      return 0x3c00u; /* 1.0 */
-   case fmul32:
-      return 0x3f800000u; /* 1.0 */
-   case fmul64:
-      return idx ? 0x3ff00000u : 0u; /* 1.0 */
-   case imin8:
-      return INT8_MAX;
-   case imin16:
-      return INT16_MAX;
-   case imin32:
-      return INT32_MAX;
-   case imin64:
-      return idx ? 0x7fffffffu : 0xffffffffu;
-   case imax8:
-      return INT8_MIN;
-   case imax16:
-      return INT16_MIN;
-   case imax32:
-      return INT32_MIN;
-   case imax64:
-      return idx ? 0x80000000u : 0;
+   case imul64: return idx ? 0 : 1;
+   case fmul16: return 0x3c00u;                /* 1.0 */
+   case fmul32: return 0x3f800000u;            /* 1.0 */
+   case fmul64: return idx ? 0x3ff00000u : 0u; /* 1.0 */
+   case imin8: return INT8_MAX;
+   case imin16: return INT16_MAX;
+   case imin32: return INT32_MAX;
+   case imin64: return idx ? 0x7fffffffu : 0xffffffffu;
+   case imax8: return INT8_MIN;
+   case imax16: return INT16_MIN;
+   case imax32: return INT32_MIN;
+   case imax64: return idx ? 0x80000000u : 0;
   case umin8:
   case umin16:
   case iand8:
-   case iand16:
-      return 0xffffffffu;
+   case iand16: return 0xffffffffu;
   case umin32:
   case umin64:
   case iand32:
-   case iand64:
-      return 0xffffffffu;
-   case fmin16:
-      return 0x7c00u; /* infinity */
-   case fmin32:
-      return 0x7f800000u; /* infinity */
-   case fmin64:
-      return idx ? 0x7ff00000u : 0u; /* infinity */
-   case fmax16:
-      return 0xfc00u; /* negative infinity */
-   case fmax32:
-      return 0xff800000u; /* negative infinity */
-   case fmax64:
-      return idx ? 0xfff00000u : 0u; /* negative infinity */
-   default:
-      unreachable("Invalid reduction operation");
-      break;
+   case iand64: return 0xffffffffu;
+   case fmin16: return 0x7c00u;                /* infinity */
+   case fmin32: return 0x7f800000u;            /* infinity */
+   case fmin64: return idx ? 0x7ff00000u : 0u; /* infinity */
+   case fmax16: return 0xfc00u;                /* negative infinity */
+   case fmax32: return 0xff800000u;            /* negative infinity */
+   case fmax64: return idx ? 0xfff00000u : 0u; /* negative infinity */
+   default: unreachable("Invalid reduction operation"); break;
   }
   return 0;
 }

-bool needs_exec_mask(const Instruction* instr) {
+bool
+needs_exec_mask(const Instruction* instr)
+{
   if (instr->isSALU() || instr->isBranch())
      return instr->reads_exec();
   if (instr->isSMEM())
@@ -479,10 +428,8 @@ bool needs_exec_mask(const Instruction* instr) {
      case aco_opcode::p_reload:
      case aco_opcode::p_logical_start:
      case aco_opcode::p_logical_end:
-      case aco_opcode::p_startpgm:
-         return false;
-      default:
-         break;
+      case aco_opcode::p_startpgm: return false;
+      default: break;
      }
   }

@@ -495,10 +442,11 @@ bool needs_exec_mask(const Instruction* instr) {
   return true;
 }

-wait_imm::wait_imm() :
-   vm(unset_counter), exp(unset_counter), lgkm(unset_counter), vs(unset_counter) {}
-wait_imm::wait_imm(uint16_t vm_, uint16_t exp_, uint16_t lgkm_, uint16_t vs_) :
-      vm(vm_), exp(exp_), lgkm(lgkm_), vs(vs_) {}
+wait_imm::wait_imm() : vm(unset_counter), exp(unset_counter), lgkm(unset_counter), vs(unset_counter)
+{}
+wait_imm::wait_imm(uint16_t vm_, uint16_t exp_, uint16_t lgkm_, uint16_t vs_)
+    : vm(vm_), exp(exp_), lgkm(lgkm_), vs(vs_)
+{}

 wait_imm::wait_imm(enum chip_class chip, uint16_t packed) : vs(unset_counter)
 {
@@ -513,7 +461,8 @@ wait_imm::wait_imm(enum chip_class chip, uint16_t packed) : vs(unset_counter)
      lgkm |= (packed >> 8) & 0x30;
 }

-uint16_t wait_imm::pack(enum chip_class chip) const
+uint16_t
+wait_imm::pack(enum chip_class chip) const
 {
   uint16_t imm = 0;
   assert(exp == unset_counter || exp <= 0x7);
@@ -536,13 +485,16 @@ uint16_t wait_imm::pack(enum chip_class chip) const
      break;
   }
   if (chip < GFX9 && vm == wait_imm::unset_counter)
-      imm |= 0xc000; /* should have no effect on pre-GFX9 and now we won't have to worry about the architecture when interpreting the immediate */
+      imm |= 0xc000; /* should have no effect on pre-GFX9 and now we won't have to worry about the
+                        architecture when interpreting the immediate */
   if (chip < GFX10 && lgkm == wait_imm::unset_counter)
-      imm |= 0x3000; /* should have no effect on pre-GFX10 and now we won't have to worry about the architecture when interpreting the immediate */
+      imm |= 0x3000; /* should have no effect on pre-GFX10 and now we won't have to worry about the
+                        architecture when interpreting the immediate */
   return imm;
 }

-bool wait_imm::combine(const wait_imm& other)
+bool
+wait_imm::combine(const wait_imm& other)
 {
   bool changed = other.vm < vm || other.exp < exp || other.lgkm < lgkm || other.vs < vs;
   vm = std::min(vm, other.vm);
@@ -552,17 +504,21 @@ bool wait_imm::combine(const wait_imm& other)
   return changed;
 }

-bool wait_imm::empty() const
+bool
+wait_imm::empty() const
 {
-   return vm == unset_counter && exp == unset_counter &&
-          lgkm == unset_counter && vs == unset_counter;
+   return vm == unset_counter && exp == unset_counter && lgkm == unset_counter &&
+          vs == unset_counter;
 }

-bool should_form_clause(const Instruction *a, const Instruction *b)
+bool
+should_form_clause(const Instruction* a, const Instruction* b)
 {
   /* Vertex attribute loads from the same binding likely load from similar addresses */
-   unsigned a_vtx_binding = a->isMUBUF() ? a->mubuf().vtx_binding : (a->isMTBUF() ? a->mtbuf().vtx_binding : 0);
-   unsigned b_vtx_binding = b->isMUBUF() ? b->mubuf().vtx_binding : (b->isMTBUF() ? b->mtbuf().vtx_binding : 0);
+   unsigned a_vtx_binding =
+      a->isMUBUF() ? a->mubuf().vtx_binding : (a->isMTBUF() ? a->mtbuf().vtx_binding : 0);
+   unsigned b_vtx_binding =
+      b->isMUBUF() ? b->mubuf().vtx_binding : (b->isMTBUF() ? b->mtbuf().vtx_binding : 0);
   if (a_vtx_binding && a_vtx_binding == b_vtx_binding)
      return true;

@@ -584,4 +540,4 @@ bool should_form_clause(const Instruction *a, const Instruction *b)
   return false;
 }

-}
+} // namespace aco