diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index 32451138cdc..05ad6d8a00c 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -3020,8 +3020,7 @@ tu_CmdBindPipeline(VkCommandBuffer commandBuffer, cmd->state.pipeline = tu_pipeline_to_graphics(pipeline); cmd->state.dirty |= TU_CMD_DIRTY_DESC_SETS | TU_CMD_DIRTY_SHADER_CONSTS | - TU_CMD_DIRTY_VS_PARAMS | TU_CMD_DIRTY_LRZ | - TU_CMD_DIRTY_PROGRAM; + TU_CMD_DIRTY_VS_PARAMS | TU_CMD_DIRTY_PROGRAM; tu_bind_vs(cmd, pipeline->shaders[MESA_SHADER_VERTEX]); tu_bind_tcs(cmd, pipeline->shaders[MESA_SHADER_TESS_CTRL]); @@ -3067,8 +3066,13 @@ tu_CmdBindPipeline(VkCommandBuffer commandBuffer, cmd->state.rp.sysmem_single_prim_mode = true; } - if (pipeline->lrz.blend_valid) - cmd->state.blend_reads_dest = pipeline->lrz.lrz_status & TU_LRZ_READS_DEST; + if (pipeline->lrz_blend.valid) { + if (cmd->state.blend_reads_dest != pipeline->lrz_blend.reads_dest) { + cmd->state.blend_reads_dest = pipeline->lrz_blend.reads_dest; + cmd->state.dirty |= TU_CMD_DIRTY_LRZ; + } + } + cmd->state.pipeline_blend_lrz = pipeline->lrz_blend.valid; if (pipeline->bandwidth.valid) cmd->state.bandwidth = pipeline->bandwidth; diff --git a/src/freedreno/vulkan/tu_cmd_buffer.h b/src/freedreno/vulkan/tu_cmd_buffer.h index f07d21105bc..7b65065380c 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.h +++ b/src/freedreno/vulkan/tu_cmd_buffer.h @@ -483,6 +483,8 @@ struct tu_cmd_state bool stencil_back_write; bool pipeline_feedback_loop_ds; + bool pipeline_blend_lrz; + /* VK_QUERY_PIPELINE_STATISTIC_CLIPPING_INVOCATIONS_BIT and * VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT are allowed to run simultaniously, * but they use the same {START,STOP}_PRIMITIVE_CTRS control. diff --git a/src/freedreno/vulkan/tu_lrz.cc b/src/freedreno/vulkan/tu_lrz.cc index 3c8baf1e9d1..7ba0f5442dd 100644 --- a/src/freedreno/vulkan/tu_lrz.cc +++ b/src/freedreno/vulkan/tu_lrz.cc @@ -558,7 +558,6 @@ static struct A6XX_GRAS_LRZ_CNTL tu6_calculate_lrz_state(struct tu_cmd_buffer *cmd, const uint32_t a) { - struct tu_pipeline *pipeline = &cmd->state.pipeline->base; const struct tu_shader *fs = cmd->state.shaders[MESA_SHADER_FRAGMENT]; bool z_test_enable = cmd->vk.dynamic_graphics_state.ds.depth.test_enable; bool z_write_enable = cmd->vk.dynamic_graphics_state.ds.depth.write_enable; @@ -585,10 +584,13 @@ tu6_calculate_lrz_state(struct tu_cmd_buffer *cmd, return gras_lrz_cntl; } + /* See comment in tu_pipeline about disabling LRZ write for blending. */ + bool reads_dest = cmd->state.blend_reads_dest; + gras_lrz_cntl.enable = true; gras_lrz_cntl.lrz_write = z_write_enable && - !(pipeline->lrz.lrz_status & TU_LRZ_FORCE_DISABLE_WRITE) && + !reads_dest && !(fs->fs.lrz.status & TU_LRZ_FORCE_DISABLE_WRITE); gras_lrz_cntl.z_test_enable = z_write_enable; gras_lrz_cntl.z_bounds_enable = z_bounds_enable; @@ -597,9 +599,6 @@ tu6_calculate_lrz_state(struct tu_cmd_buffer *cmd, gras_lrz_cntl.disable_on_wrong_dir = cmd->state.lrz.gpu_dir_tracking; - /* See comment in tu_pipeline about disabling LRZ write for blending. */ - bool reads_dest = cmd->state.blend_reads_dest; - /* LRZ is disabled until it is cleared, which means that one "wrong" * depth test or shader could disable LRZ until depth buffer is cleared. */ diff --git a/src/freedreno/vulkan/tu_pipeline.cc b/src/freedreno/vulkan/tu_pipeline.cc index b933273c8f6..af246ae304b 100644 --- a/src/freedreno/vulkan/tu_pipeline.cc +++ b/src/freedreno/vulkan/tu_pipeline.cc @@ -2159,7 +2159,8 @@ tu_pipeline_builder_parse_libraries(struct tu_pipeline_builder *builder, if (library->state & VK_GRAPHICS_PIPELINE_LIBRARY_FRAGMENT_OUTPUT_INTERFACE_BIT_EXT) { pipeline->output = library->base.output; - pipeline->lrz.lrz_status |= library->base.lrz.lrz_status; + pipeline->lrz_blend.reads_dest |= library->base.lrz_blend.reads_dest; + pipeline->lrz_blend.valid |= library->base.lrz_blend.valid; pipeline->prim_order = library->base.prim_order; } @@ -2956,13 +2957,12 @@ static const enum mesa_vk_dynamic_graphics_state tu_blend_lrz_state[] = { }; static void -tu_emit_blend_lrz(struct tu_lrz_pipeline *lrz, +tu_emit_blend_lrz(struct tu_lrz_blend *lrz, const struct vk_color_blend_state *cb, const struct vk_render_pass_state *rp) { - if (tu6_calc_blend_lrz(cb, rp)) - lrz->lrz_status |= TU_LRZ_FORCE_DISABLE_WRITE | TU_LRZ_READS_DEST; - lrz->blend_valid = true; + lrz->reads_dest = tu6_calc_blend_lrz(cb, rp); + lrz->valid = true; } static const enum mesa_vk_dynamic_graphics_state tu_blend_state[] = { @@ -3417,7 +3417,7 @@ tu_pipeline_builder_emit_state(struct tu_pipeline_builder *builder, builder->graphics_state.ms->alpha_to_one_enable, builder->graphics_state.ms->sample_mask); if (EMIT_STATE(blend_lrz, attachments_valid)) - tu_emit_blend_lrz(&pipeline->lrz, cb, + tu_emit_blend_lrz(&pipeline->lrz_blend, cb, builder->graphics_state.rp); if (EMIT_STATE(bandwidth, attachments_valid)) tu_calc_bandwidth(&pipeline->bandwidth, cb, @@ -3605,7 +3605,7 @@ tu_emit_draw_state(struct tu_cmd_buffer *cmd) cmd->vk.dynamic_graphics_state.ms.sample_mask); if (EMIT_STATE(blend_lrz) || ((cmd->state.dirty & TU_CMD_DIRTY_SUBPASS) && - !cmd->state.pipeline->base.lrz.blend_valid)) { + !cmd->state.pipeline_blend_lrz)) { bool blend_reads_dest = tu6_calc_blend_lrz(&cmd->vk.dynamic_graphics_state.cb, &cmd->state.vk_rp); if (blend_reads_dest != cmd->state.blend_reads_dest) { diff --git a/src/freedreno/vulkan/tu_pipeline.h b/src/freedreno/vulkan/tu_pipeline.h index 174cff39991..485430c3bd3 100644 --- a/src/freedreno/vulkan/tu_pipeline.h +++ b/src/freedreno/vulkan/tu_pipeline.h @@ -36,11 +36,10 @@ enum tu_dynamic_state struct cache_entry; -struct tu_lrz_pipeline +struct tu_lrz_blend { - uint32_t lrz_status; - - bool blend_valid; + bool valid; + bool reads_dest; }; struct tu_bandwidth @@ -158,7 +157,7 @@ struct tu_pipeline struct tu_program_state program; - struct tu_lrz_pipeline lrz; + struct tu_lrz_blend lrz_blend; struct tu_bandwidth bandwidth; void *executables_mem_ctx;