tu: Rewrite remaining pipeline LRZ handling
Now that the FS-specific parts are split out, the only remaining part is the blend state part. Use the same state that we use for dynamic blending for static blending, eliminating the last use of the pipeline in the LRZ code. While we're at it fix a bug where dynamic blending didn't always disable LRZ writes (even though it only mattered with a non-conformant debug flag because we invalidated LRZ anyway). Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25276>
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@@ -3020,8 +3020,7 @@ tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
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cmd->state.pipeline = tu_pipeline_to_graphics(pipeline);
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cmd->state.dirty |= TU_CMD_DIRTY_DESC_SETS | TU_CMD_DIRTY_SHADER_CONSTS |
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TU_CMD_DIRTY_VS_PARAMS | TU_CMD_DIRTY_LRZ |
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TU_CMD_DIRTY_PROGRAM;
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TU_CMD_DIRTY_VS_PARAMS | TU_CMD_DIRTY_PROGRAM;
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tu_bind_vs(cmd, pipeline->shaders[MESA_SHADER_VERTEX]);
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tu_bind_tcs(cmd, pipeline->shaders[MESA_SHADER_TESS_CTRL]);
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@@ -3067,8 +3066,13 @@ tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
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cmd->state.rp.sysmem_single_prim_mode = true;
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}
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if (pipeline->lrz.blend_valid)
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cmd->state.blend_reads_dest = pipeline->lrz.lrz_status & TU_LRZ_READS_DEST;
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if (pipeline->lrz_blend.valid) {
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if (cmd->state.blend_reads_dest != pipeline->lrz_blend.reads_dest) {
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cmd->state.blend_reads_dest = pipeline->lrz_blend.reads_dest;
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cmd->state.dirty |= TU_CMD_DIRTY_LRZ;
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}
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}
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cmd->state.pipeline_blend_lrz = pipeline->lrz_blend.valid;
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if (pipeline->bandwidth.valid)
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cmd->state.bandwidth = pipeline->bandwidth;
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@@ -483,6 +483,8 @@ struct tu_cmd_state
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bool stencil_back_write;
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bool pipeline_feedback_loop_ds;
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bool pipeline_blend_lrz;
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/* VK_QUERY_PIPELINE_STATISTIC_CLIPPING_INVOCATIONS_BIT and
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* VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT are allowed to run simultaniously,
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* but they use the same {START,STOP}_PRIMITIVE_CTRS control.
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@@ -558,7 +558,6 @@ static struct A6XX_GRAS_LRZ_CNTL
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tu6_calculate_lrz_state(struct tu_cmd_buffer *cmd,
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const uint32_t a)
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{
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struct tu_pipeline *pipeline = &cmd->state.pipeline->base;
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const struct tu_shader *fs = cmd->state.shaders[MESA_SHADER_FRAGMENT];
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bool z_test_enable = cmd->vk.dynamic_graphics_state.ds.depth.test_enable;
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bool z_write_enable = cmd->vk.dynamic_graphics_state.ds.depth.write_enable;
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@@ -585,10 +584,13 @@ tu6_calculate_lrz_state(struct tu_cmd_buffer *cmd,
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return gras_lrz_cntl;
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}
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/* See comment in tu_pipeline about disabling LRZ write for blending. */
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bool reads_dest = cmd->state.blend_reads_dest;
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gras_lrz_cntl.enable = true;
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gras_lrz_cntl.lrz_write =
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z_write_enable &&
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!(pipeline->lrz.lrz_status & TU_LRZ_FORCE_DISABLE_WRITE) &&
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!reads_dest &&
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!(fs->fs.lrz.status & TU_LRZ_FORCE_DISABLE_WRITE);
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gras_lrz_cntl.z_test_enable = z_write_enable;
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gras_lrz_cntl.z_bounds_enable = z_bounds_enable;
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@@ -597,9 +599,6 @@ tu6_calculate_lrz_state(struct tu_cmd_buffer *cmd,
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gras_lrz_cntl.disable_on_wrong_dir = cmd->state.lrz.gpu_dir_tracking;
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/* See comment in tu_pipeline about disabling LRZ write for blending. */
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bool reads_dest = cmd->state.blend_reads_dest;
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/* LRZ is disabled until it is cleared, which means that one "wrong"
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* depth test or shader could disable LRZ until depth buffer is cleared.
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*/
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@@ -2159,7 +2159,8 @@ tu_pipeline_builder_parse_libraries(struct tu_pipeline_builder *builder,
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if (library->state &
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VK_GRAPHICS_PIPELINE_LIBRARY_FRAGMENT_OUTPUT_INTERFACE_BIT_EXT) {
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pipeline->output = library->base.output;
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pipeline->lrz.lrz_status |= library->base.lrz.lrz_status;
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pipeline->lrz_blend.reads_dest |= library->base.lrz_blend.reads_dest;
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pipeline->lrz_blend.valid |= library->base.lrz_blend.valid;
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pipeline->prim_order = library->base.prim_order;
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}
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@@ -2956,13 +2957,12 @@ static const enum mesa_vk_dynamic_graphics_state tu_blend_lrz_state[] = {
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};
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static void
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tu_emit_blend_lrz(struct tu_lrz_pipeline *lrz,
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tu_emit_blend_lrz(struct tu_lrz_blend *lrz,
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const struct vk_color_blend_state *cb,
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const struct vk_render_pass_state *rp)
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{
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if (tu6_calc_blend_lrz(cb, rp))
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lrz->lrz_status |= TU_LRZ_FORCE_DISABLE_WRITE | TU_LRZ_READS_DEST;
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lrz->blend_valid = true;
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lrz->reads_dest = tu6_calc_blend_lrz(cb, rp);
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lrz->valid = true;
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}
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static const enum mesa_vk_dynamic_graphics_state tu_blend_state[] = {
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@@ -3417,7 +3417,7 @@ tu_pipeline_builder_emit_state(struct tu_pipeline_builder *builder,
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builder->graphics_state.ms->alpha_to_one_enable,
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builder->graphics_state.ms->sample_mask);
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if (EMIT_STATE(blend_lrz, attachments_valid))
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tu_emit_blend_lrz(&pipeline->lrz, cb,
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tu_emit_blend_lrz(&pipeline->lrz_blend, cb,
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builder->graphics_state.rp);
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if (EMIT_STATE(bandwidth, attachments_valid))
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tu_calc_bandwidth(&pipeline->bandwidth, cb,
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@@ -3605,7 +3605,7 @@ tu_emit_draw_state(struct tu_cmd_buffer *cmd)
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cmd->vk.dynamic_graphics_state.ms.sample_mask);
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if (EMIT_STATE(blend_lrz) ||
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((cmd->state.dirty & TU_CMD_DIRTY_SUBPASS) &&
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!cmd->state.pipeline->base.lrz.blend_valid)) {
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!cmd->state.pipeline_blend_lrz)) {
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bool blend_reads_dest = tu6_calc_blend_lrz(&cmd->vk.dynamic_graphics_state.cb,
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&cmd->state.vk_rp);
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if (blend_reads_dest != cmd->state.blend_reads_dest) {
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@@ -36,11 +36,10 @@ enum tu_dynamic_state
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struct cache_entry;
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struct tu_lrz_pipeline
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struct tu_lrz_blend
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{
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uint32_t lrz_status;
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bool blend_valid;
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bool valid;
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bool reads_dest;
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};
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struct tu_bandwidth
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@@ -158,7 +157,7 @@ struct tu_pipeline
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struct tu_program_state program;
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struct tu_lrz_pipeline lrz;
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struct tu_lrz_blend lrz_blend;
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struct tu_bandwidth bandwidth;
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void *executables_mem_ctx;
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