OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

radeonsi/gfx10: enable image stores with DCC

Browse Source 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Marek Olšák
2019-06-28 23:48:14 -04:00
parent 5b50fb9b7f
commit 1d3bffaf9c
4 changed files with 10 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/gallium/drivers/radeonsi/si_descriptors.c
View File

@@ -739,7 +739,7 @@ static void si_set_shader_image_desc(struct si_context *ctx,
assert(fmask_desc || tex->surface.fmask_size == 0);
if (uses_dcc && !skip_decompress &&
(view->access & PIPE_IMAGE_ACCESS_WRITE ||
((ctx->chip_class <= GFX9 && view->access & PIPE_IMAGE_ACCESS_WRITE) ||
!vi_dcc_formats_compatible(screen, res->b.b.format, view->format))) {
/* If DCC can't be disabled, at least decompress it.
* The decompression is relatively cheap if the surface

4
src/gallium/drivers/radeonsi/si_shader_internal.h
View File

@@ -347,8 +347,8 @@ LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx,
enum ac_descriptor_type type);
LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
LLVMValueRef list, LLVMValueRef index,
enum ac_descriptor_type desc_type, bool dcc_off,
bool bindless);
enum ac_descriptor_type desc_type,
bool uses_store, bool bindless);
void si_load_system_value(struct si_shader_context *ctx,
unsigned index,

5
src/gallium/drivers/radeonsi/si_shader_nir.c
View File

@@ -1031,7 +1031,6 @@ si_nir_load_sampler_desc(struct ac_shader_abi *abi,
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
LLVMBuilderRef builder = ctx->ac.builder;
unsigned const_index = base_index + constant_index;
bool dcc_off = write;
assert(!descriptor_set);
assert(!image || desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
@@ -1049,7 +1048,7 @@ si_nir_load_sampler_desc(struct ac_shader_abi *abi,
LLVMConstInt(ctx->i64, 2, 0), "");
return si_load_image_desc(ctx, list, dynamic_index, desc_type,
dcc_off, true);
write, true);
}
/* Since bindless handle arithmetic can contain an unsigned integer
@@ -1088,7 +1087,7 @@ si_nir_load_sampler_desc(struct ac_shader_abi *abi,
index = LLVMBuildSub(ctx->ac.builder,
LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
index, "");
return si_load_image_desc(ctx, list, index, desc_type, dcc_off, false);
return si_load_image_desc(ctx, list, index, desc_type, write, false);
}
index = LLVMBuildAdd(ctx->ac.builder, index,

10
src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
View File

@@ -176,8 +176,8 @@ static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
LLVMValueRef list, LLVMValueRef index,
enum ac_descriptor_type desc_type, bool dcc_off,
bool bindless)
enum ac_descriptor_type desc_type,
bool uses_store, bool bindless)
{
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef rsrc;
@@ -196,7 +196,8 @@ LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
else
rsrc = ac_build_load_to_sgpr(&ctx->ac, list, index);
if (desc_type == AC_DESC_IMAGE && dcc_off)
if (ctx->ac.chip_class <= GFX9 &&
desc_type == AC_DESC_IMAGE && uses_store)
rsrc = force_dcc_off(ctx, rsrc);
return rsrc;
}
@@ -215,7 +216,6 @@ image_fetch_rsrc(
LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
ctx->param_samplers_and_images);
LLVMValueRef index;
bool dcc_off = is_store;
if (!image->Register.Indirect) {
index = LLVMConstInt(ctx->i32,
@@ -259,7 +259,7 @@ image_fetch_rsrc(
*rsrc = si_load_image_desc(ctx, rsrc_ptr, index,
target == TGSI_TEXTURE_BUFFER ? AC_DESC_BUFFER : AC_DESC_IMAGE,
dcc_off, bindless);
is_store, bindless);
}
static void image_fetch_coords(