diff --git a/src/amd/common/ac_shader_args.h b/src/amd/common/ac_shader_args.h
index 9d8112b409f..4f2dba2ba28 100644
--- a/src/amd/common/ac_shader_args.h
+++ b/src/amd/common/ac_shader_args.h
@@ -143,6 +143,7 @@ struct ac_shader_args {
    unsigned base_inline_push_consts;
    struct ac_arg view_index;
    struct ac_arg sbt_descriptors;
+   struct ac_arg ray_launch_size;
 };
 
 void ac_add_arg(struct ac_shader_args *info, enum ac_arg_regfile regfile, unsigned registers,
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index c3fb726d97f..ab21294c3a2 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -6573,6 +6573,18 @@ radv_CmdTraceRaysKHR(VkCommandBuffer commandBuffer,
       return;
    }
 
+   struct radv_userdata_info *loc = radv_lookup_user_sgpr(
+      cmd_buffer->state.rt_pipeline, MESA_SHADER_COMPUTE, AC_UD_CS_RAY_LAUNCH_SIZE);
+
+   if (loc->sgpr_idx != -1) {
+      assert(loc->num_sgprs == 3);
+
+      radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
+      radeon_emit(cmd_buffer->cs, width);
+      radeon_emit(cmd_buffer->cs, height);
+      radeon_emit(cmd_buffer->cs, depth);
+   }
+
    radv_rt_dispatch(cmd_buffer, &info);
 }
 
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index debc52fc88f..8971f654ef9 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -171,6 +171,7 @@ enum radv_ud_index {
    AC_UD_PS_MAX_UD,
    AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
    AC_UD_CS_SBT_DESCRIPTORS,
+   AC_UD_CS_RAY_LAUNCH_SIZE,
    AC_UD_CS_MAX_UD,
    AC_UD_GS_MAX_UD,
    AC_UD_TCS_MAX_UD,
@@ -346,6 +347,7 @@ struct radv_shader_info {
       unsigned block_size[3];
 
       bool uses_sbt;
+      bool uses_ray_launch_size;
    } cs;
    struct {
       uint64_t tes_inputs_read;
diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c
index 70439ab274f..625c7a46e45 100644
--- a/src/amd/vulkan/radv_shader_args.c
+++ b/src/amd/vulkan/radv_shader_args.c
@@ -190,6 +190,8 @@ allocate_user_sgprs(struct radv_shader_args *args, gl_shader_stage stage, bool h
          user_sgpr_count += 1;
       if (args->shader_info->cs.uses_grid_size)
          user_sgpr_count += 3;
+      if (args->shader_info->cs.uses_ray_launch_size)
+         user_sgpr_count += 3;
       break;
    case MESA_SHADER_FRAGMENT:
       user_sgpr_count += args->shader_info->ps.needs_sample_positions;
@@ -497,6 +499,10 @@ radv_declare_shader_args(struct radv_shader_args *args, gl_shader_stage stage,
          ac_add_arg(&args->ac, AC_ARG_SGPR, 3, AC_ARG_INT, &args->ac.num_work_groups);
       }
 
+      if (args->shader_info->cs.uses_ray_launch_size) {
+         ac_add_arg(&args->ac, AC_ARG_SGPR, 3, AC_ARG_INT, &args->ac.ray_launch_size);
+      }
+
       for (int i = 0; i < 3; i++) {
          if (args->shader_info->cs.uses_block_id[i]) {
             ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.workgroup_ids[i]);
@@ -715,6 +721,9 @@ radv_declare_shader_args(struct radv_shader_args *args, gl_shader_stage stage,
       if (args->shader_info->cs.uses_grid_size) {
          set_loc_shader(args, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, 3);
       }
+      if (args->shader_info->cs.uses_ray_launch_size) {
+         set_loc_shader(args, AC_UD_CS_RAY_LAUNCH_SIZE, &user_sgpr_idx, 3);
+      }
       break;
    case MESA_SHADER_VERTEX:
       set_vs_specific_input_locs(args, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index 428f51823bd..31ded5e304d 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -161,6 +161,9 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
    case nir_intrinsic_load_num_workgroups:
       info->cs.uses_grid_size = true;
       break;
+   case nir_intrinsic_load_ray_launch_size:
+      info->cs.uses_ray_launch_size = true;
+      break;
    case nir_intrinsic_load_local_invocation_id:
    case nir_intrinsic_load_workgroup_id: {
       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);