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nir/fold_16bit_tex_image: Add type granularity for dst folding

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Some HW may be able to fold only some of dst types, e.g.
for Adreno folding i32 -> i16 could cause a different result since
folded variant clamps the result instead of masking it.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20396>
This commit is contained in:
Danylo Piliaiev
2022-12-20 16:23:15 +01:00
parent c5231025be
commit 1c9ee30838
6 changed files with 12 additions and 8 deletions
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src/amd/vulkan/radv_pipeline.c
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@@ -3745,7 +3745,7 @@ radv_postprocess_nir(struct radv_pipeline *pipeline,
};
struct nir_fold_16bit_tex_image_options fold_16bit_options = {
.rounding_mode = nir_rounding_mode_rtne,
.fold_tex_dest = true,
.fold_tex_dest_types = nir_type_float | nir_type_uint | nir_type_int,
.fold_image_load_store_data = true,
.fold_image_srcs = !radv_use_llvm_for_stage(device, stage->stage),
.fold_srcs_options_count = separate_g16 ? 2 : 1,