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anv/query: Move the available bits to the front

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We're about to make slots variable-length and always having the
available bits at the front makes certain operations substantially
easier once we do that.

Reviewed-By: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
Jason Ekstrand
2017-03-14 17:56:05 -07:00
parent 9d43afa3dc
commit 1c797af2c6
2 changed files with 19 additions and 28 deletions
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2
src/intel/vulkan/anv_private.h
View File

@@ -2014,9 +2014,9 @@ struct anv_render_pass {
}; };
struct anv_query_pool_slot { struct anv_query_pool_slot {
uint64_t available;
uint64_t begin; uint64_t begin;
uint64_t end; uint64_t end;
uint64_t available;
}; };
struct anv_query_pool { struct anv_query_pool {

45
src/intel/vulkan/genX_query.c
View File

@@ -232,22 +232,13 @@ void genX(CmdResetQueryPool)(
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool); ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
for (uint32_t i = 0; i < queryCount; i++) { for (uint32_t i = 0; i < queryCount; i++) {
switch (pool->type) { anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdm) {
case VK_QUERY_TYPE_OCCLUSION: sdm.Address = (struct anv_address) {
case VK_QUERY_TYPE_TIMESTAMP: { .bo = &pool->bo,
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdm) { .offset = (firstQuery + i) * sizeof(struct anv_query_pool_slot),
sdm.Address = (struct anv_address) { };
.bo = &pool->bo, sdm.DataDWord0 = 0;
.offset = (firstQuery + i) * sizeof(struct anv_query_pool_slot) + sdm.DataDWord1 = 0;
offsetof(struct anv_query_pool_slot, available),
};
sdm.DataDWord0 = 0;
sdm.DataDWord1 = 0;
}
break;
}
default:
assert(!"Invalid query type");
} }
} }
} }
@@ -278,7 +269,7 @@ void genX(CmdBeginQuery)(
switch (pool->type) { switch (pool->type) {
case VK_QUERY_TYPE_OCCLUSION: case VK_QUERY_TYPE_OCCLUSION:
emit_ps_depth_count(cmd_buffer, &pool->bo, emit_ps_depth_count(cmd_buffer, &pool->bo,
query * sizeof(struct anv_query_pool_slot)); query * sizeof(struct anv_query_pool_slot) + 8);
break; break;
case VK_QUERY_TYPE_PIPELINE_STATISTICS: case VK_QUERY_TYPE_PIPELINE_STATISTICS:
@@ -298,10 +289,10 @@ void genX(CmdEndQuery)(
switch (pool->type) { switch (pool->type) {
case VK_QUERY_TYPE_OCCLUSION: case VK_QUERY_TYPE_OCCLUSION:
emit_ps_depth_count(cmd_buffer, &pool->bo, emit_ps_depth_count(cmd_buffer, &pool->bo,
query * sizeof(struct anv_query_pool_slot) + 8); query * sizeof(struct anv_query_pool_slot) + 16);
emit_query_availability(cmd_buffer, &pool->bo, emit_query_availability(cmd_buffer, &pool->bo,
query * sizeof(struct anv_query_pool_slot) + 16); query * sizeof(struct anv_query_pool_slot));
break; break;
case VK_QUERY_TYPE_PIPELINE_STATISTICS: case VK_QUERY_TYPE_PIPELINE_STATISTICS:
@@ -328,11 +319,11 @@ void genX(CmdWriteTimestamp)(
case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT: case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), srm) { anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), srm) {
srm.RegisterAddress = TIMESTAMP; srm.RegisterAddress = TIMESTAMP;
srm.MemoryAddress = (struct anv_address) { &pool->bo, offset }; srm.MemoryAddress = (struct anv_address) { &pool->bo, offset + 8 };
} }
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), srm) { anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), srm) {
srm.RegisterAddress = TIMESTAMP + 4; srm.RegisterAddress = TIMESTAMP + 4;
srm.MemoryAddress = (struct anv_address) { &pool->bo, offset + 4 }; srm.MemoryAddress = (struct anv_address) { &pool->bo, offset + 12 };
} }
break; break;
@@ -341,7 +332,7 @@ void genX(CmdWriteTimestamp)(
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.DestinationAddressType = DAT_PPGTT; pc.DestinationAddressType = DAT_PPGTT;
pc.PostSyncOperation = WriteTimestamp; pc.PostSyncOperation = WriteTimestamp;
pc.Address = (struct anv_address) { &pool->bo, offset }; pc.Address = (struct anv_address) { &pool->bo, offset + 8 };
if (GEN_GEN == 9 && cmd_buffer->device->info.gt == 4) if (GEN_GEN == 9 && cmd_buffer->device->info.gt == 4)
pc.CommandStreamerStallEnable = true; pc.CommandStreamerStallEnable = true;
@@ -349,7 +340,7 @@ void genX(CmdWriteTimestamp)(
break; break;
} }
emit_query_availability(cmd_buffer, &pool->bo, offset + 16); emit_query_availability(cmd_buffer, &pool->bo, offset);
} }
#if GEN_GEN > 7 || GEN_IS_HASWELL #if GEN_GEN > 7 || GEN_IS_HASWELL
@@ -446,9 +437,9 @@ void genX(CmdCopyQueryPoolResults)(
switch (pool->type) { switch (pool->type) {
case VK_QUERY_TYPE_OCCLUSION: case VK_QUERY_TYPE_OCCLUSION:
emit_load_alu_reg_u64(&cmd_buffer->batch, emit_load_alu_reg_u64(&cmd_buffer->batch,
CS_GPR(0), &pool->bo, slot_offset); CS_GPR(0), &pool->bo, slot_offset + 8);
emit_load_alu_reg_u64(&cmd_buffer->batch, emit_load_alu_reg_u64(&cmd_buffer->batch,
CS_GPR(1), &pool->bo, slot_offset + 8); CS_GPR(1), &pool->bo, slot_offset + 16);
/* FIXME: We need to clamp the result for 32 bit. */ /* FIXME: We need to clamp the result for 32 bit. */
@@ -461,7 +452,7 @@ void genX(CmdCopyQueryPoolResults)(
case VK_QUERY_TYPE_TIMESTAMP: case VK_QUERY_TYPE_TIMESTAMP:
emit_load_alu_reg_u64(&cmd_buffer->batch, emit_load_alu_reg_u64(&cmd_buffer->batch,
CS_GPR(2), &pool->bo, slot_offset); CS_GPR(2), &pool->bo, slot_offset + 8);
break; break;
default: default:
@@ -473,7 +464,7 @@ void genX(CmdCopyQueryPoolResults)(
if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) { if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
emit_load_alu_reg_u64(&cmd_buffer->batch, CS_GPR(0), emit_load_alu_reg_u64(&cmd_buffer->batch, CS_GPR(0),
&pool->bo, slot_offset + 16); &pool->bo, slot_offset);
if (flags & VK_QUERY_RESULT_64_BIT) if (flags & VK_QUERY_RESULT_64_BIT)
store_query_result(&cmd_buffer->batch, store_query_result(&cmd_buffer->batch,
CS_GPR(0), buffer->bo, dst_offset + 8, flags); CS_GPR(0), buffer->bo, dst_offset + 8, flags);