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radv: convert radv_color_blend_info to vk_color_blend_state

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18015>
This commit is contained in:
Samuel Pitoiset
2022-08-10 09:44:34 +02:00
parent 8b6a9e8a68
commit 1c4026501c
2 changed files with 165 additions and 225 deletions
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141
src/amd/vulkan/radv_pipeline.c
View File

@@ -666,10 +666,12 @@ radv_pipeline_init_blend_state(struct radv_graphics_pipeline *pipeline,
const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
int i;
if (info->cb.logic_op_enable)
cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(info->cb.logic_op));
if (state->cb) {
if (state->cb->logic_op_enable)
cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(state->cb->logic_op));
else
cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
}
if (device->instance->debug_flags & RADV_DEBUG_NO_ATOC_DITHERING)
{
@@ -690,20 +692,21 @@ radv_pipeline_init_blend_state(struct radv_graphics_pipeline *pipeline,
}
blend.cb_target_mask = 0;
for (i = 0; i < info->cb.att_count; i++) {
if (state->cb) {
for (i = 0; i < state->cb->attachment_count; i++) {
unsigned blend_cntl = 0;
unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
VkBlendOp eqRGB = info->cb.att[i].color_blend_op;
VkBlendFactor srcRGB = info->cb.att[i].src_color_blend_factor;
VkBlendFactor dstRGB = info->cb.att[i].dst_color_blend_factor;
VkBlendOp eqA = info->cb.att[i].alpha_blend_op;
VkBlendFactor srcA = info->cb.att[i].src_alpha_blend_factor;
VkBlendFactor dstA = info->cb.att[i].dst_alpha_blend_factor;
VkBlendOp eqRGB = state->cb->attachments[i].color_blend_op;
VkBlendFactor srcRGB = state->cb->attachments[i].src_color_blend_factor;
VkBlendFactor dstRGB = state->cb->attachments[i].dst_color_blend_factor;
VkBlendOp eqA = state->cb->attachments[i].alpha_blend_op;
VkBlendFactor srcA = state->cb->attachments[i].src_alpha_blend_factor;
VkBlendFactor dstA = state->cb->attachments[i].dst_alpha_blend_factor;
blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
if (!info->cb.att[i].color_write_mask)
if (!state->cb->attachments[i].write_mask)
continue;
/* Ignore other blend targets if dual-source blending
@@ -712,9 +715,9 @@ radv_pipeline_init_blend_state(struct radv_graphics_pipeline *pipeline,
if (blend.mrt0_is_dual_src)
continue;
blend.cb_target_mask |= (unsigned)info->cb.att[i].color_write_mask << (4 * i);
blend.cb_target_mask |= (unsigned)state->cb->attachments[i].write_mask << (4 * i);
blend.cb_target_enabled_4bit |= 0xfu << (4 * i);
if (!info->cb.att[i].blend_enable) {
if (!state->cb->attachments[i].blend_enable) {
blend.cb_blend_control[i] = blend_cntl;
continue;
}
@@ -795,11 +798,12 @@ radv_pipeline_init_blend_state(struct radv_graphics_pipeline *pipeline,
dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
blend.need_src_alpha |= 1 << i;
}
for (i = info->cb.att_count; i < 8; i++) {
for (i = state->cb->attachment_count; i < 8; i++) {
blend.cb_blend_control[i] = 0;
blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
}
}
if (device->physical_device->rad_info.has_rbplus) {
/* Disable RB+ blend optimizations for dual source blending. */
@@ -813,7 +817,7 @@ radv_pipeline_init_blend_state(struct radv_graphics_pipeline *pipeline,
/* RB+ doesn't work with dual source blending, logic op and
* RESOLVE.
*/
if (blend.mrt0_is_dual_src || info->cb.logic_op_enable ||
if (blend.mrt0_is_dual_src || (state->cb && state->cb->logic_op_enable) ||
(device->physical_device->rad_info.gfx_level >= GFX11 && blend.blend_enable_4bit))
cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
}
@@ -955,7 +959,7 @@ radv_pipeline_out_of_order_rast(struct radv_graphics_pipeline *pipeline,
return false;
/* Be conservative if a logic operation is enabled with color buffers. */
if (colormask && info->cb.logic_op_enable)
if (colormask && state->cb && state->cb->logic_op_enable)
return false;
/* Be conservative if an extended dynamic depth/stencil state is
@@ -1301,12 +1305,14 @@ radv_dynamic_state_mask(VkDynamicState state)
static bool
radv_pipeline_is_blend_enabled(const struct radv_graphics_pipeline *pipeline,
const struct radv_color_blend_info *cb_info)
const struct vk_color_blend_state *cb)
{
for (uint32_t i = 0; i < cb_info->att_count; i++) {
if (cb_info->att[i].color_write_mask && cb_info->att[i].blend_enable)
if (cb) {
for (uint32_t i = 0; i < cb->attachment_count; i++) {
if (cb->attachments[i].write_mask && cb->attachments[i].blend_enable)
return true;
}
}
return false;
}
@@ -1366,7 +1372,7 @@ radv_pipeline_needed_dynamic_state(const struct radv_graphics_pipeline *pipeline
if (!radv_is_vrs_enabled(pipeline, state))
states &= ~RADV_DYNAMIC_FRAGMENT_SHADING_RATE;
if (!has_color_att || !radv_pipeline_is_blend_enabled(pipeline, &info->cb))
if (!has_color_att || !radv_pipeline_is_blend_enabled(pipeline, state->cb))
states &= ~RADV_DYNAMIC_BLEND_CONSTANTS;
if (!has_color_att)
@@ -1588,62 +1594,6 @@ radv_pipeline_init_rendering_info(struct radv_graphics_pipeline *pipeline,
return info;
}
static struct radv_color_blend_info
radv_pipeline_init_color_blend_info(struct radv_graphics_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
const VkPipelineColorBlendStateCreateInfo *cb = pCreateInfo->pColorBlendState;
const VkPipelineRenderingCreateInfo *ri =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO);
struct radv_color_blend_info info = {0};
bool has_color_att = false;
for (uint32_t i = 0; i < ri->colorAttachmentCount; ++i) {
if (ri->pColorAttachmentFormats[i] != VK_FORMAT_UNDEFINED) {
has_color_att = true;
break;
}
}
if (radv_is_raster_enabled(pipeline, pCreateInfo) && has_color_att) {
for (uint32_t i = 0; i < cb->attachmentCount; i++) {
const VkPipelineColorBlendAttachmentState *att = &cb->pAttachments[i];
info.att[i].color_write_mask = att->colorWriteMask;
info.att[i].blend_enable = att->blendEnable;
info.att[i].color_blend_op = att->colorBlendOp;
info.att[i].alpha_blend_op = att->alphaBlendOp;
info.att[i].src_color_blend_factor = att->srcColorBlendFactor;
info.att[i].dst_color_blend_factor = att->dstColorBlendFactor;
info.att[i].src_alpha_blend_factor = att->srcAlphaBlendFactor;
info.att[i].dst_alpha_blend_factor = att->dstAlphaBlendFactor;
}
info.att_count = cb->attachmentCount;
if (!(pipeline->dynamic_states & RADV_DYNAMIC_BLEND_CONSTANTS)) {
for (uint32_t i = 0; i < 4; i++) {
info.blend_constants[i] = cb->blendConstants[i];
}
}
info.logic_op_enable = cb->logicOpEnable;
if (info.logic_op_enable && !(pipeline->dynamic_states & RADV_DYNAMIC_LOGIC_OP))
info.logic_op = cb->logicOp;
const VkPipelineColorWriteCreateInfoEXT *color_write_info =
vk_find_struct_const(cb->pNext, PIPELINE_COLOR_WRITE_CREATE_INFO_EXT);
if (color_write_info && !(pipeline->dynamic_states & RADV_DYNAMIC_COLOR_WRITE_ENABLE)) {
for (uint32_t i = 0; i < color_write_info->attachmentCount; i++) {
info.color_write_enable |= color_write_info->pColorWriteEnables[i] ? (1u << i) : 0;
}
} else {
info.color_write_enable = 0xffu;
}
}
return info;
}
static struct radv_graphics_pipeline_info
radv_pipeline_init_graphics_info(struct radv_graphics_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
@@ -1656,7 +1606,6 @@ radv_pipeline_init_graphics_info(struct radv_graphics_pipeline *pipeline,
}
info.ri = radv_pipeline_init_rendering_info(pipeline, pCreateInfo);
info.cb = radv_pipeline_init_color_blend_info(pipeline, pCreateInfo);
/* VK_AMD_mixed_attachment_samples */
const VkAttachmentSampleCountInfoAMD *sample_info =
@@ -1729,7 +1678,7 @@ radv_pipeline_init_dynamic_state(struct radv_graphics_pipeline *pipeline,
* created against does not use any color attachments.
*/
if (states & RADV_DYNAMIC_BLEND_CONSTANTS) {
typed_memcpy(dynamic->blend_constants, info->cb.blend_constants, 4);
typed_memcpy(dynamic->blend_constants, state->cb->blend_constants, 4);
}
if (states & RADV_DYNAMIC_CULL_MODE) {
@@ -1854,15 +1803,15 @@ radv_pipeline_init_dynamic_state(struct radv_graphics_pipeline *pipeline,
}
if (radv_pipeline_has_color_attachments(&info->ri) && states & RADV_DYNAMIC_LOGIC_OP) {
if (info->cb.logic_op_enable) {
dynamic->logic_op = si_translate_blend_logic_op(info->cb.logic_op);
if (state->cb->logic_op_enable) {
dynamic->logic_op = si_translate_blend_logic_op(state->cb->logic_op);
} else {
dynamic->logic_op = V_028808_ROP3_COPY;
}
}
if (states & RADV_DYNAMIC_COLOR_WRITE_ENABLE) {
u_foreach_bit(i, info->cb.color_write_enable) {
u_foreach_bit(i, state->cb->color_write_enables) {
dynamic->color_write_enable |= 0xfu << (i * 4);
}
}
@@ -4799,7 +4748,8 @@ struct radv_bin_size_entry {
static VkExtent2D
radv_gfx9_compute_bin_size(const struct radv_graphics_pipeline *pipeline,
const struct radv_graphics_pipeline_info *info)
const struct radv_graphics_pipeline_info *info,
const struct vk_graphics_pipeline_state *state)
{
const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
static const struct radv_bin_size_entry color_size_table[][3][9] = {
@@ -5023,8 +4973,9 @@ radv_gfx9_compute_bin_size(const struct radv_graphics_pipeline *pipeline,
unsigned effective_samples = total_samples;
unsigned color_bytes_per_pixel = 0;
if (state->cb) {
for (unsigned i = 0; i < info->ri.color_att_count; i++) {
if (!info->cb.att[i].color_write_mask)
if (!state->cb->attachments[i].write_mask)
continue;
if (info->ri.color_att_formats[i] == VK_FORMAT_UNDEFINED)
@@ -5032,6 +4983,7 @@ radv_gfx9_compute_bin_size(const struct radv_graphics_pipeline *pipeline,
color_bytes_per_pixel += vk_format_get_blocksize(info->ri.color_att_formats[i]);
}
}
/* MSAA images typically don't use all samples all the time. */
if (effective_samples >= 2 && ps_iter_samples <= 1)
@@ -5063,7 +5015,8 @@ radv_gfx9_compute_bin_size(const struct radv_graphics_pipeline *pipeline,
static VkExtent2D
radv_gfx10_compute_bin_size(const struct radv_graphics_pipeline *pipeline,
const struct radv_graphics_pipeline_info *info)
const struct radv_graphics_pipeline_info *info,
const struct vk_graphics_pipeline_state *state)
{
const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
VkExtent2D extent = {512, 512};
@@ -5091,8 +5044,9 @@ radv_gfx10_compute_bin_size(const struct radv_graphics_pipeline *pipeline,
unsigned color_bytes_per_pixel = 0;
unsigned fmask_bytes_per_pixel = 0;
if (state->cb) {
for (unsigned i = 0; i < info->ri.color_att_count; i++) {
if (!info->cb.att[i].color_write_mask)
if (!state->cb->attachments[i].write_mask)
continue;
if (info->ri.color_att_formats[i] == VK_FORMAT_UNDEFINED)
@@ -5106,6 +5060,7 @@ radv_gfx10_compute_bin_size(const struct radv_graphics_pipeline *pipeline,
fmask_bytes_per_pixel += fmask_array[samples_log];
}
}
}
color_bytes_per_pixel *= total_samples;
color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
@@ -5148,7 +5103,8 @@ radv_gfx10_compute_bin_size(const struct radv_graphics_pipeline *pipeline,
static void
radv_pipeline_init_disabled_binning_state(struct radv_graphics_pipeline *pipeline,
const struct radv_graphics_pipeline_info *info)
const struct radv_graphics_pipeline_info *info,
const struct vk_graphics_pipeline_state *state)
{
const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
uint32_t pa_sc_binner_cntl_0 = S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
@@ -5157,8 +5113,9 @@ radv_pipeline_init_disabled_binning_state(struct radv_graphics_pipeline *pipelin
if (pdevice->rad_info.gfx_level >= GFX10) {
unsigned min_bytes_per_pixel = 0;
if (state->cb) {
for (unsigned i = 0; i < info->ri.color_att_count; i++) {
if (!info->cb.att[i].color_write_mask)
if (!state->cb->attachments[i].write_mask)
continue;
if (info->ri.color_att_formats[i] == VK_FORMAT_UNDEFINED)
@@ -5168,6 +5125,7 @@ radv_pipeline_init_disabled_binning_state(struct radv_graphics_pipeline *pipelin
if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
min_bytes_per_pixel = bytes;
}
}
pa_sc_binner_cntl_0 =
S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) | S_028C44_BIN_SIZE_X(0) |
@@ -5209,7 +5167,8 @@ radv_get_binning_settings(const struct radv_physical_device *pdev)
static void
radv_pipeline_init_binning_state(struct radv_graphics_pipeline *pipeline,
const struct radv_blend_state *blend,
const struct radv_graphics_pipeline_info *info)
const struct radv_graphics_pipeline_info *info,
const struct vk_graphics_pipeline_state *state)
{
const struct radv_device *device = pipeline->base.device;
@@ -5218,9 +5177,9 @@ radv_pipeline_init_binning_state(struct radv_graphics_pipeline *pipeline,
VkExtent2D bin_size;
if (device->physical_device->rad_info.gfx_level >= GFX10) {
bin_size = radv_gfx10_compute_bin_size(pipeline, info);
bin_size = radv_gfx10_compute_bin_size(pipeline, info, state);
} else if (device->physical_device->rad_info.gfx_level == GFX9) {
bin_size = radv_gfx9_compute_bin_size(pipeline, info);
bin_size = radv_gfx9_compute_bin_size(pipeline, info, state);
} else
unreachable("Unhandled generation for binning bin size calculation");
@@ -5239,7 +5198,7 @@ radv_pipeline_init_binning_state(struct radv_graphics_pipeline *pipeline,
pipeline->binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
} else
radv_pipeline_init_disabled_binning_state(pipeline, info);
radv_pipeline_init_disabled_binning_state(pipeline, info, state);
}
static void
@@ -6747,7 +6706,7 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
if (!radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH))
radv_pipeline_init_vertex_input_state(pipeline, &info);
radv_pipeline_init_binning_state(pipeline, &blend, &info);
radv_pipeline_init_binning_state(pipeline, &blend, &info, &state);
radv_pipeline_init_shader_stages_state(pipeline);
radv_pipeline_init_scratch(device, &pipeline->base);

19
src/amd/vulkan/radv_private.h
View File

@@ -1970,29 +1970,10 @@ struct radv_rendering_info {
VkFormat stencil_att_format;
};
struct radv_color_blend_info {
bool logic_op_enable;
uint8_t att_count;
VkLogicOp logic_op;
uint32_t color_write_enable;
float blend_constants[4];
struct {
uint8_t color_write_mask;
bool blend_enable;
VkBlendOp color_blend_op;
VkBlendOp alpha_blend_op;
VkBlendFactor src_color_blend_factor;
VkBlendFactor dst_color_blend_factor;
VkBlendFactor src_alpha_blend_factor;
VkBlendFactor dst_alpha_blend_factor;
} att[MAX_RTS];
};
struct radv_graphics_pipeline_info {
struct radv_vertex_input_info vi;
struct radv_rendering_info ri;
struct radv_color_blend_info cb;
/* VK_AMD_mixed_attachment_samples */
uint8_t color_att_samples;