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radv: zero-initialize radv_shader_info earlier for graphics pipeline

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This should allow us to remove a big memset when compiling a
graphics pipeline. This is mostly for imported NIR stages which
don't go through radv_pipeline_stage_init().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20947>
This commit is contained in:
Samuel Pitoiset
2023-03-09 17:28:28 +01:00
parent 67635bb3e3
commit 1c286db14e
2 changed files with 6 additions and 1 deletions
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5
src/amd/vulkan/radv_pipeline.c
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@@ -2541,7 +2541,6 @@ radv_fill_shader_info(struct radv_graphics_pipeline *pipeline,
bool consider_force_vrs = radv_consider_force_vrs(pipeline, noop_fs, stages);
radv_foreach_stage(i, active_nir_stages) {
radv_nir_shader_info_init(&stages[i].info);
radv_nir_shader_info_pass(device, stages[i].nir, pipeline_layout, pipeline_key,
pipeline->base.type,
i == pipeline->last_vgt_api_stage && consider_force_vrs,
@@ -3554,6 +3553,10 @@ radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline,
bool optimize_conservatively = pipeline_key->optimisations_disabled;
radv_foreach_stage(i, active_nir_stages) {
radv_nir_shader_info_init(&stages[i].info);
}
/* Determine if shaders uses NGG before linking because it's needed for some NIR pass. */
radv_fill_shader_info_ngg(pipeline, pipeline_key, stages);