diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index a3803127646..e27274cd357 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -1244,6 +1244,35 @@ iris_init_render_context(struct iris_batch *batch)
}
#endif
+#if GFX_VER == 12
+ iris_emit_reg(batch, GENX(FF_MODE2), reg) {
+ /* On Alchemist, the FF_MODE2 docs for the GS timer say:
+ *
+ * "The timer value must be set to 224."
+ *
+ * and Wa_16011163337 indicates this is the case for all Gfx12 parts,
+ * and that this is necessary to avoid hanging the HS/DS units. It
+ * also clarifies that 224 is literally 0xE0 in the bits, not 7*32=224.
+ *
+ * The HS timer docs also have the same quote for Alchemist. I am
+ * unaware of a reason it needs to be set to 224 on Tigerlake, but
+ * we do so for consistency if nothing else.
+ *
+ * For the TDS timer value, the docs say:
+ *
+ * "For best performance, a value of 4 should be programmed."
+ *
+ * i915 also sets it this way on Tigerlake due to workarounds.
+ *
+ * The default VS timer appears to be 0, so we leave it at that.
+ */
+ reg.GSTimerValue = 224;
+ reg.HSTimerValue = 224;
+ reg.TDSTimerValue = 4;
+ reg.VSTimerValue = 0;
+ }
+#endif
+
#if INTEL_NEEDS_WORKAROUND_1508744258
/* The suggested workaround is:
*
diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml
index a611b5445c4..d69e22bb811 100644
--- a/src/intel/genxml/gen12.xml
+++ b/src/intel/genxml/gen12.xml
@@ -6957,6 +6957,12 @@
+
+
+
+
+
+
diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index fd330fe4371..26bf74140b5 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -7445,6 +7445,12 @@
+
+
+
+
+
+
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index 16f95b758a5..cb364f0b90d 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -484,6 +484,35 @@ init_render_queue_state(struct anv_queue *queue)
}
#endif
+#if GFX_VER == 12
+ anv_batch_write_reg(&batch, GENX(FF_MODE2), reg) {
+ /* On Alchemist, the FF_MODE2 docs for the GS timer say:
+ *
+ * "The timer value must be set to 224."
+ *
+ * and Wa_16011163337 indicates this is the case for all Gfx12 parts,
+ * and that this is necessary to avoid hanging the HS/DS units. It
+ * also clarifies that 224 is literally 0xE0 in the bits, not 7*32=224.
+ *
+ * The HS timer docs also have the same quote for Alchemist. I am
+ * unaware of a reason it needs to be set to 224 on Tigerlake, but
+ * we do so for consistency if nothing else.
+ *
+ * For the TDS timer value, the docs say:
+ *
+ * "For best performance, a value of 4 should be programmed."
+ *
+ * i915 also sets it this way on Tigerlake due to workarounds.
+ *
+ * The default VS timer appears to be 0, so we leave it at that.
+ */
+ reg.GSTimerValue = 224;
+ reg.HSTimerValue = 224;
+ reg.TDSTimerValue = 4;
+ reg.VSTimerValue = 0;
+ }
+#endif
+
#if INTEL_NEEDS_WA_1508744258
/* Disable RHWO by setting 0x7010[14] by default except during resolve
* pass.