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iris: Make various classes inherit from u_threaded_context base classes

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u_threaded_context requires various objects to inherit from a new
threaded_foo base class rather than directly from pipe_foo.  This
patch does most of the mechanical changes required for that.

It also initializes the new threaded_resource fields.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8964>
This commit is contained in:
Kenneth Graunke
2021-02-08 16:39:42 -08:00
parent 3358c7125a
commit 1b1c857248
8 changed files with 76 additions and 65 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/gallium/drivers/iris/iris_blit.c
View File

@@ -488,10 +488,10 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
struct blorp_surf src_surf, dst_surf;
iris_blorp_surf_for_resource(&screen->isl_dev, &src_surf,
&src_res->base, src_aux_usage,
&src_res->base.b, src_aux_usage,
info->src.level, false);
iris_blorp_surf_for_resource(&screen->isl_dev, &dst_surf,
&dst_res->base, dst_aux_usage,
&dst_res->base.b, dst_aux_usage,
info->dst.level, true);
iris_resource_prepare_render(ice, dst_res, info->dst.level,
@@ -503,8 +503,8 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
if (iris_batch_references(batch, src_res->bo))
tex_cache_flush_hack(batch, src_fmt.fmt, src_res->surf.format);
if (dst_res->base.target == PIPE_BUFFER) {
util_range_add(&dst_res->base, &dst_res->valid_buffer_range,
if (dst_res->base.b.target == PIPE_BUFFER) {
util_range_add(&dst_res->base.b, &dst_res->valid_buffer_range,
dst_x0, dst_x1);
}
@@ -638,7 +638,7 @@ iris_copy_region(struct blorp_context *blorp,
tex_cache_flush_hack(batch, ISL_FORMAT_UNSUPPORTED, src_res->surf.format);
if (dst->target == PIPE_BUFFER)
util_range_add(&dst_res->base, &dst_res->valid_buffer_range, dstx, dstx + src_box->width);
util_range_add(&dst_res->base.b, &dst_res->valid_buffer_range, dstx, dstx + src_box->width);
if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
struct blorp_address src_addr = {
@@ -766,8 +766,8 @@ iris_resource_copy_region(struct pipe_context *ctx,
iris_get_depth_stencil_resources(p_src, &junk, &s_src_res);
iris_get_depth_stencil_resources(p_dst, &junk, &s_dst_res);
iris_copy_region(&ice->blorp, batch, &s_dst_res->base, dst_level, dstx,
dsty, dstz, &s_src_res->base, src_level, src_box);
iris_copy_region(&ice->blorp, batch, &s_dst_res->base.b, dst_level, dstx,
dsty, dstz, &s_src_res->base.b, src_level, src_box);
}
iris_flush_and_dirty_for_history(ice, batch, dst,

6
src/gallium/drivers/iris/iris_clear.c
View File

@@ -354,7 +354,7 @@ clear_color(struct iris_context *ice,
}
if (p_res->target == PIPE_BUFFER)
util_range_add(&res->base, &res->valid_buffer_range, box->x, box->x + box->width);
util_range_add(&res->base.b, &res->valid_buffer_range, box->x, box->x + box->width);
iris_batch_maybe_flush(batch, 1500);
@@ -577,7 +577,7 @@ clear_depth_stencil(struct iris_context *ice,
aux_usage);
iris_emit_buffer_barrier_for(batch, z_res->bo, IRIS_DOMAIN_DEPTH_WRITE);
iris_blorp_surf_for_resource(&batch->screen->isl_dev, &z_surf,
&z_res->base, aux_usage, level, true);
&z_res->base.b, aux_usage, level, true);
}
uint8_t stencil_mask = clear_stencil && stencil_res ? 0xff : 0;
@@ -587,7 +587,7 @@ clear_depth_stencil(struct iris_context *ice,
iris_emit_buffer_barrier_for(batch, stencil_res->bo,
IRIS_DOMAIN_DEPTH_WRITE);
iris_blorp_surf_for_resource(&batch->screen->isl_dev,
&stencil_surf, &stencil_res->base,
&stencil_surf, &stencil_res->base.b,
stencil_res->aux.usage, level, true);
}

1
src/gallium/drivers/iris/iris_context.h
View File

@@ -28,6 +28,7 @@
#include "util/set.h"
#include "util/slab.h"
#include "util/u_debug.h"
#include "util/u_threaded_context.h"
#include "intel/blorp/blorp.h"
#include "intel/dev/gen_debug.h"
#include "intel/common/gen_l3_config.h"

2
src/gallium/drivers/iris/iris_query.c
View File

@@ -52,6 +52,8 @@
#define SO_NUM_PRIMS_WRITTEN(n) (GENX(SO_NUM_PRIMS_WRITTEN0_num) + (n) * 8)
struct iris_query {
struct threaded_query b;
enum pipe_query_type type;
int index;

20
src/gallium/drivers/iris/iris_resolve.c
View File

@@ -95,7 +95,7 @@ resolve_sampler_views(struct iris_context *ice,
const int i = u_bit_scan(&views);
struct iris_sampler_view *isv = shs->textures[i];
if (isv->res->base.target != PIPE_BUFFER) {
if (isv->res->base.b.target != PIPE_BUFFER) {
if (consider_framebuffer) {
disable_rb_aux_buffer(ice, draw_aux_buffer_disabled, isv->res,
isv->view.base_level, isv->view.levels,
@@ -128,7 +128,7 @@ resolve_image_views(struct iris_context *ice,
struct pipe_image_view *pview = &shs->image[i].base;
struct iris_resource *res = (void *) pview->resource;
if (res->base.target != PIPE_BUFFER) {
if (res->base.b.target != PIPE_BUFFER) {
if (consider_framebuffer) {
disable_rb_aux_buffer(ice, draw_aux_buffer_disabled,
res, pview->u.tex.level, 1,
@@ -392,7 +392,7 @@ iris_resolve_color(struct iris_context *ice,
struct blorp_surf surf;
iris_blorp_surf_for_resource(&batch->screen->isl_dev, &surf,
&res->base, res->aux.usage, level, true);
&res->base.b, res->aux.usage, level, true);
iris_batch_maybe_flush(batch, 1500);
@@ -440,7 +440,7 @@ iris_mcs_partial_resolve(struct iris_context *ice,
struct blorp_surf surf;
iris_blorp_surf_for_resource(&batch->screen->isl_dev, &surf,
&res->base, res->aux.usage, 0, true);
&res->base.b, res->aux.usage, 0, true);
iris_emit_buffer_barrier_for(batch, res->bo, IRIS_DOMAIN_RENDER_WRITE);
struct blorp_batch blorp_batch;
@@ -550,7 +550,7 @@ iris_hiz_exec(struct iris_context *ice,
struct blorp_surf surf;
iris_blorp_surf_for_resource(&batch->screen->isl_dev, &surf,
&res->base, res->aux.usage, level, true);
&res->base.b, res->aux.usage, level, true);
struct blorp_batch blorp_batch;
enum blorp_batch_flags flags = 0;
@@ -598,10 +598,10 @@ iris_resource_level_has_hiz(const struct iris_resource *res, uint32_t level)
* For LOD == 0, we can grow the dimensions to make it work.
*/
if (level > 0) {
if (u_minify(res->base.width0, level) & 7)
if (u_minify(res->base.b.width0, level) & 7)
return false;
if (u_minify(res->base.height0, level) & 3)
if (u_minify(res->base.b.height0, level) & 3)
return false;
}
@@ -614,7 +614,7 @@ iris_resource_check_level_layer(UNUSED const struct iris_resource *res,
UNUSED uint32_t level, UNUSED uint32_t layer)
{
assert(level < res->surf.levels);
assert(layer < util_num_layers(&res->base, level));
assert(layer < util_num_layers(&res->base.b, level));
}
static inline uint32_t
@@ -637,7 +637,7 @@ static inline uint32_t
miptree_layer_range_length(const struct iris_resource *res, uint32_t level,
uint32_t start_layer, uint32_t num_layers)
{
assert(level <= res->base.last_level);
assert(level <= res->base.b.last_level);
const uint32_t total_num_layers = iris_get_num_logical_layers(res, level);
assert(start_layer < total_num_layers);
@@ -812,7 +812,7 @@ iris_resource_set_aux_state(struct iris_context *ice,
if (aux_state == ISL_AUX_STATE_CLEAR ||
aux_state == ISL_AUX_STATE_COMPRESSED_CLEAR ||
aux_state == ISL_AUX_STATE_PARTIAL_CLEAR) {
iris_mark_dirty_dmabuf(ice, &res->base);
iris_mark_dirty_dmabuf(ice, &res->base.b);
}
}
}

75
src/gallium/drivers/iris/iris_resource.c
View File

@@ -394,17 +394,18 @@ iris_resource_disable_aux(struct iris_resource *res)
static void
iris_resource_destroy(struct pipe_screen *screen,
struct pipe_resource *resource)
struct pipe_resource *p_res)
{
struct iris_resource *res = (struct iris_resource *)resource;
struct iris_resource *res = (struct iris_resource *) p_res;
if (resource->target == PIPE_BUFFER)
if (p_res->target == PIPE_BUFFER)
util_range_destroy(&res->valid_buffer_range);
iris_resource_disable_aux(res);
threaded_resource_deinit(p_res);
iris_bo_unreference(res->bo);
iris_pscreen_unref(res->base.screen);
iris_pscreen_unref(res->base.b.screen);
free(res);
}
@@ -417,9 +418,10 @@ iris_alloc_resource(struct pipe_screen *pscreen,
if (!res)
return NULL;
res->base = *templ;
res->base.screen = iris_pscreen_ref(pscreen);
pipe_reference_init(&res->base.reference, 1);
res->base.b = *templ;
res->base.b.screen = iris_pscreen_ref(pscreen);
pipe_reference_init(&res->base.b.reference, 1);
threaded_resource_init(&res->base.b);
res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE;
@@ -820,7 +822,7 @@ iris_resource_finish_aux_import(struct pipe_screen *pscreen,
struct iris_resource *r[4] = { NULL, };
unsigned num_planes = 0;
unsigned num_main_planes = 0;
for (struct pipe_resource *p_res = &res->base; p_res; p_res = p_res->next) {
for (struct pipe_resource *p_res = &res->base.b; p_res; p_res = p_res->next) {
r[num_planes] = (struct iris_resource *)p_res;
num_main_planes += r[num_planes++]->bo != NULL;
}
@@ -899,14 +901,16 @@ iris_resource_create_for_buffer(struct pipe_screen *pscreen,
res->bo = iris_bo_alloc(screen->bufmgr, name, templ->width0, memzone);
if (!res->bo) {
iris_resource_destroy(pscreen, &res->base);
iris_resource_destroy(pscreen, &res->base.b);
return NULL;
}
if (templ->bind & PIPE_BIND_SHARED)
if (templ->bind & PIPE_BIND_SHARED) {
iris_bo_make_external(res->bo);
res->base.is_shared = true;
}
return &res->base;
return &res->base.b;
}
static struct pipe_resource *
@@ -998,16 +1002,17 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen,
map_aux_addresses(screen, res, res->surf.format, 0);
}
if (templ->bind & PIPE_BIND_SHARED)
if (templ->bind & PIPE_BIND_SHARED) {
iris_bo_make_external(res->bo);
res->base.is_shared = true;
}
return &res->base;
return &res->base.b;
fail:
fprintf(stderr, "XXX: resource creation failed\n");
iris_resource_destroy(pscreen, &res->base);
iris_resource_destroy(pscreen, &res->base.b);
return NULL;
}
static struct pipe_resource *
@@ -1048,17 +1053,18 @@ iris_resource_from_user_memory(struct pipe_screen *pscreen,
assert(templ->target == PIPE_BUFFER);
res->internal_format = templ->format;
res->base.is_user_ptr = true;
res->bo = iris_bo_create_userptr(bufmgr, "user",
user_memory, templ->width0,
IRIS_MEMZONE_OTHER);
if (!res->bo) {
iris_resource_destroy(pscreen, &res->base);
iris_resource_destroy(pscreen, &res->base.b);
return NULL;
}
util_range_add(&res->base, &res->valid_buffer_range, 0, templ->width0);
util_range_add(&res->base.b, &res->valid_buffer_range, 0, templ->width0);
return &res->base;
return &res->base.b;
}
static struct pipe_resource *
@@ -1124,10 +1130,10 @@ iris_resource_from_handle(struct pipe_screen *pscreen,
res->bo = NULL;
}
return &res->base;
return &res->base.b;
fail:
iris_resource_destroy(pscreen, &res->base);
iris_resource_destroy(pscreen, &res->base.b);
return NULL;
}
@@ -1255,7 +1261,7 @@ iris_resource_get_param(struct pipe_screen *pscreen,
static bool
iris_resource_get_handle(struct pipe_screen *pscreen,
struct pipe_context *ctx,
struct pipe_context *unused_ctx,
struct pipe_resource *resource,
struct winsys_handle *whandle,
unsigned usage)
@@ -1420,7 +1426,7 @@ static void
iris_map_copy_region(struct iris_transfer *map)
{
struct pipe_screen *pscreen = &map->batch->screen->base;
struct pipe_transfer *xfer = &map->base;
struct pipe_transfer *xfer = &map->base.b;
struct pipe_box *box = &xfer->box;
struct iris_resource *res = (void *) xfer->resource;
@@ -1593,7 +1599,7 @@ s8_offset(uint32_t stride, uint32_t x, uint32_t y)
static void
iris_unmap_s8(struct iris_transfer *map)
{
struct pipe_transfer *xfer = &map->base;
struct pipe_transfer *xfer = &map->base.b;
const struct pipe_box *box = &xfer->box;
struct iris_resource *res = (struct iris_resource *) xfer->resource;
struct isl_surf *surf = &res->surf;
@@ -1625,7 +1631,7 @@ iris_unmap_s8(struct iris_transfer *map)
static void
iris_map_s8(struct iris_transfer *map)
{
struct pipe_transfer *xfer = &map->base;
struct pipe_transfer *xfer = &map->base.b;
const struct pipe_box *box = &xfer->box;
struct iris_resource *res = (struct iris_resource *) xfer->resource;
struct isl_surf *surf = &res->surf;
@@ -1697,7 +1703,7 @@ tile_extents(const struct isl_surf *surf,
static void
iris_unmap_tiled_memcpy(struct iris_transfer *map)
{
struct pipe_transfer *xfer = &map->base;
struct pipe_transfer *xfer = &map->base.b;
const struct pipe_box *box = &xfer->box;
struct iris_resource *res = (struct iris_resource *) xfer->resource;
struct isl_surf *surf = &res->surf;
@@ -1726,7 +1732,7 @@ iris_unmap_tiled_memcpy(struct iris_transfer *map)
static void
iris_map_tiled_memcpy(struct iris_transfer *map)
{
struct pipe_transfer *xfer = &map->base;
struct pipe_transfer *xfer = &map->base.b;
const struct pipe_box *box = &xfer->box;
struct iris_resource *res = (struct iris_resource *) xfer->resource;
struct isl_surf *surf = &res->surf;
@@ -1771,13 +1777,13 @@ iris_map_tiled_memcpy(struct iris_transfer *map)
static void
iris_map_direct(struct iris_transfer *map)
{
struct pipe_transfer *xfer = &map->base;
struct pipe_transfer *xfer = &map->base.b;
struct pipe_box *box = &xfer->box;
struct iris_resource *res = (struct iris_resource *) xfer->resource;
void *ptr = iris_bo_map(map->dbg, res->bo, xfer->usage & MAP_FLAGS);
if (res->base.target == PIPE_BUFFER) {
if (res->base.b.target == PIPE_BUFFER) {
xfer->stride = 0;
xfer->layer_stride = 0;
@@ -1807,7 +1813,7 @@ can_promote_to_async(const struct iris_resource *res,
* initialized with useful data, then we can safely promote this write
* to be unsynchronized. This helps the common pattern of appending data.
*/
return res->base.target == PIPE_BUFFER && (usage & PIPE_MAP_WRITE) &&
return res->base.b.target == PIPE_BUFFER && (usage & PIPE_MAP_WRITE) &&
!(usage & TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED) &&
!util_ranges_intersect(&res->valid_buffer_range, box->x,
box->x + box->width);
@@ -1860,11 +1866,12 @@ iris_transfer_map(struct pipe_context *ctx,
return NULL;
struct iris_transfer *map = slab_alloc(&ice->transfer_pool);
struct pipe_transfer *xfer = &map->base;
if (!map)
return NULL;
struct pipe_transfer *xfer = &map->base.b;
memset(map, 0, sizeof(*map));
map->dbg = &ice->dbg;
@@ -1879,7 +1886,7 @@ iris_transfer_map(struct pipe_context *ctx,
box->x + box->width);
if (usage & PIPE_MAP_WRITE)
util_range_add(&res->base, &res->valid_buffer_range, box->x, box->x + box->width);
util_range_add(&res->base.b, &res->valid_buffer_range, box->x, box->x + box->width);
/* Avoid using GPU copies for persistent/coherent buffers, as the idea
* there is to access them simultaneously on the CPU & GPU. This also
@@ -1964,14 +1971,14 @@ iris_transfer_flush_region(struct pipe_context *ctx,
uint32_t history_flush = 0;
if (res->base.target == PIPE_BUFFER) {
if (res->base.b.target == PIPE_BUFFER) {
if (map->staging)
history_flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
if (map->dest_had_defined_contents)
history_flush |= iris_flush_bits_for_history(ice, res);
util_range_add(&res->base, &res->valid_buffer_range, box->x, box->x + box->width);
util_range_add(&res->base.b, &res->valid_buffer_range, box->x, box->x + box->width);
}
if (history_flush & ~PIPE_CONTROL_CS_STALL) {
@@ -2150,7 +2157,7 @@ iris_flush_and_dirty_for_history(struct iris_context *ice,
uint32_t extra_flags,
const char *reason)
{
if (res->base.target != PIPE_BUFFER)
if (res->base.b.target != PIPE_BUFFER)
return;
uint32_t flush = iris_flush_bits_for_history(ice, res) | extra_flags;

5
src/gallium/drivers/iris/iris_resource.h
View File

@@ -26,6 +26,7 @@
#include "pipe/p_state.h"
#include "util/u_inlines.h"
#include "util/u_range.h"
#include "util/u_threaded_context.h"
#include "intel/isl/isl.h"
#include "iris_bufmgr.h"
@@ -50,7 +51,7 @@ struct iris_format_info {
* They contain the storage (BO) and layout information (ISL surface).
*/
struct iris_resource {
struct pipe_resource base;
struct threaded_resource base;
enum pipe_format internal_format;
/**
@@ -261,7 +262,7 @@ struct iris_surface {
* Transfer object - information about a buffer mapping.
*/
struct iris_transfer {
struct pipe_transfer base;
struct threaded_transfer base;
struct pipe_debug_callback *dbg;
void *buffer;
void *ptr;

18
src/gallium/drivers/iris/iris_state.c
View File

@@ -2451,7 +2451,7 @@ iris_create_sampler_view(struct pipe_context *ctx,
iris_get_depth_stencil_resources(tex, &zres, &sres);
tex = util_format_has_depth(desc) ? &zres->base : &sres->base;
tex = util_format_has_depth(desc) ? &zres->base.b : &sres->base.b;
}
isv->res = (struct iris_resource *) tex;
@@ -2814,7 +2814,7 @@ iris_set_shader_images(struct pipe_context *ctx,
void *map = iv->surface_state.cpu;
if (res->base.target != PIPE_BUFFER) {
if (res->base.b.target != PIPE_BUFFER) {
struct isl_view view = {
.format = isl_fmt,
.base_level = img->u.tex.level,
@@ -2847,7 +2847,7 @@ iris_set_shader_images(struct pipe_context *ctx,
&image_params[start_slot + i],
&res->surf, &view);
} else {
util_range_add(&res->base, &res->valid_buffer_range, img->u.buf.offset,
util_range_add(&res->base.b, &res->valid_buffer_range, img->u.buf.offset,
img->u.buf.offset + img->u.buf.size);
fill_buffer_surface_state(&screen->isl_dev, res, map,
@@ -3431,7 +3431,7 @@ iris_set_shader_buffers(struct pipe_context *ctx,
struct pipe_shader_buffer *ssbo = &shs->ssbo[start_slot + i];
struct iris_state_ref *surf_state =
&shs->ssbo_surf_state[start_slot + i];
pipe_resource_reference(&ssbo->buffer, &res->base);
pipe_resource_reference(&ssbo->buffer, &res->base.b);
ssbo->buffer_offset = buffers[i].buffer_offset;
ssbo->buffer_size =
MIN2(buffers[i].buffer_size, res->bo->size - ssbo->buffer_offset);
@@ -3445,7 +3445,7 @@ iris_set_shader_buffers(struct pipe_context *ctx,
res->bind_history |= PIPE_BIND_SHADER_BUFFER;
res->bind_stages |= 1 << stage;
util_range_add(&res->base, &res->valid_buffer_range, ssbo->buffer_offset,
util_range_add(&res->base.b, &res->valid_buffer_range, ssbo->buffer_offset,
ssbo->buffer_offset + ssbo->buffer_size);
} else {
pipe_resource_reference(&shs->ssbo[start_slot + i].buffer, NULL);
@@ -3515,7 +3515,7 @@ iris_set_vertex_buffers(struct pipe_context *ctx,
vb.AddressModifyEnable = true;
vb.BufferPitch = buffer->stride;
if (res) {
vb.BufferSize = res->base.width0 - (int) buffer->buffer_offset;
vb.BufferSize = res->base.b.width0 - (int) buffer->buffer_offset;
vb.BufferStartingAddress =
ro_bo(NULL, res->bo->gtt_offset + (int) buffer->buffer_offset);
vb.MOCS = iris_mocs(res->bo, &screen->isl_dev,
@@ -3706,7 +3706,7 @@ iris_create_stream_output_target(struct pipe_context *ctx,
cso->base.buffer_size = buffer_size;
cso->base.context = ctx;
util_range_add(&res->base, &res->valid_buffer_range, buffer_offset,
util_range_add(&res->base.b, &res->valid_buffer_range, buffer_offset,
buffer_offset + buffer_size);
return &cso->base;
@@ -7163,7 +7163,7 @@ iris_rebind_buffer(struct iris_context *ice,
struct pipe_context *ctx = &ice->ctx;
struct iris_genx_state *genx = ice->state.genx;
assert(res->base.target == PIPE_BUFFER);
assert(res->base.b.target == PIPE_BUFFER);
/* Buffers can't be framebuffer attachments, nor display related,
* and we don't have upstream Clover support.
@@ -7254,7 +7254,7 @@ iris_rebind_buffer(struct iris_context *ice,
if (res->bo == iris_resource_bo(ssbo->buffer)) {
struct pipe_shader_buffer buf = {
.buffer = &res->base,
.buffer = &res->base.b,
.buffer_offset = ssbo->buffer_offset,
.buffer_size = ssbo->buffer_size,
};