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nir,ac/llvm: add nir_intrinsic_load_half_line_width_amd

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Used by AMD GPU NGG line culling. We could use nir load
line width and viewport scale to calculate this in shader,
but this way needs expensive divide ops.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
This commit is contained in:
Qiang Yu
2022-06-06 16:37:16 +08:00
committed by Marge Bot
parent 0c2b824f67
commit 1aef9c8318
3 changed files with 5 additions and 0 deletions
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1
src/amd/llvm/ac_nir_to_llvm.c
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@@ -3581,6 +3581,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
case nir_intrinsic_load_lshs_vertex_stride_amd: case nir_intrinsic_load_lshs_vertex_stride_amd:
case nir_intrinsic_load_tcs_num_patches_amd: case nir_intrinsic_load_tcs_num_patches_amd:
case nir_intrinsic_load_hs_out_patch_data_offset_amd: case nir_intrinsic_load_hs_out_patch_data_offset_amd:
case nir_intrinsic_load_clip_half_line_width_amd:
result = ctx->abi->intrinsic_load(ctx->abi, instr->intrinsic); result = ctx->abi->intrinsic_load(ctx->abi, instr->intrinsic);
break; break;
case nir_intrinsic_load_vertex_id_zero_base: { case nir_intrinsic_load_vertex_id_zero_base: {

1
src/compiler/nir/nir_divergence_analysis.c
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@@ -181,6 +181,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr)
case nir_intrinsic_load_ray_num_dss_rt_stacks_intel: case nir_intrinsic_load_ray_num_dss_rt_stacks_intel:
case nir_intrinsic_load_lshs_vertex_stride_amd: case nir_intrinsic_load_lshs_vertex_stride_amd:
case nir_intrinsic_load_hs_out_patch_data_offset_amd: case nir_intrinsic_load_hs_out_patch_data_offset_amd:
case nir_intrinsic_load_clip_half_line_width_amd:
is_divergent = false; is_divergent = false;
break; break;

3
src/compiler/nir/nir_intrinsics.py
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@@ -1416,6 +1416,9 @@ system_value("lshs_vertex_stride_amd", 1)
# Per patch data offset in HS VRAM output buffer # Per patch data offset in HS VRAM output buffer
system_value("hs_out_patch_data_offset_amd", 1) system_value("hs_out_patch_data_offset_amd", 1)
# line_width * 0.5 / abs(viewport_scale[2])
system_value("clip_half_line_width_amd", 2)
# V3D-specific instrinc for tile buffer color reads. # V3D-specific instrinc for tile buffer color reads.
# #
# The hardware requires that we read the samples and components of a pixel # The hardware requires that we read the samples and components of a pixel