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radeonsi: r600: d3d12: st: Use NIR lowering for tg4 offset arrays instead of GLSL lowering

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I think I got all the drivers that need updating.  This is only
necessary in drivers that support GLSL 4.00 / GL_ARB_gpu_shader5 and
have PIPE_CAP_TEXTURE_GATHER_OFFSETS = 0.

v2: Don't (accidentally) condition tg4 offsets lowering on tex rect
lowering.  Noticed by Qiang.

v3: Add missing bool() cast.

v4: don't use designated initializers

Fixes: 640f909862 ("glsl: add _texture related sparse texture builtin functions")
Closes: #6365
Tested-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16547>
This commit is contained in:
Ian Romanick
2022-05-17 08:18:26 -07:00
committed by Marge Bot
parent dbd022f2ab
commit 1aacd9492d
5 changed files with 9 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/gallium/drivers/d3d12/d3d12_compiler.cpp
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@@ -1173,6 +1173,7 @@ select_shader_variant(struct d3d12_selection_context *sel_ctx, d3d12_shader_sele
tex_options.saturate_r = key.tex_saturate_r; tex_options.saturate_r = key.tex_saturate_r;
tex_options.saturate_t = key.tex_saturate_t; tex_options.saturate_t = key.tex_saturate_t;
tex_options.lower_invalid_implicit_lod = true; tex_options.lower_invalid_implicit_lod = true;
tex_options.lower_tg4_offsets = true;
NIR_PASS_V(new_nir_variant, nir_lower_tex, &tex_options); NIR_PASS_V(new_nir_variant, nir_lower_tex, &tex_options);
} }

1
src/gallium/drivers/r600/sfn/sfn_nir.cpp
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@@ -681,6 +681,7 @@ int r600_shader_from_nir(struct r600_context *rctx,
lower_tex_options.lower_txp = ~0u; lower_tex_options.lower_txp = ~0u;
lower_tex_options.lower_txf_offset = true; lower_tex_options.lower_txf_offset = true;
lower_tex_options.lower_invalid_implicit_lod = true; lower_tex_options.lower_invalid_implicit_lod = true;
lower_tex_options.lower_tg4_offsets = true;
NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options); NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
NIR_PASS_V(sel->nir, r600_nir_lower_txl_txf_array_or_cube); NIR_PASS_V(sel->nir, r600_nir_lower_txl_txf_array_or_cube);

1
src/gallium/drivers/radeonsi/si_shader_nir.c
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@@ -251,6 +251,7 @@ static void si_lower_nir(struct si_screen *sscreen, struct nir_shader *nir)
.lower_txp = ~0u, .lower_txp = ~0u,
.lower_txs_cube_array = true, .lower_txs_cube_array = true,
.lower_invalid_implicit_lod = true, .lower_invalid_implicit_lod = true,
.lower_tg4_offsets = true,
}; };
NIR_PASS_V(nir, nir_lower_tex, &lower_tex_options); NIR_PASS_V(nir, nir_lower_tex, &lower_tex_options);

2
src/mesa/state_tracker/st_glsl_to_ir.cpp
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@@ -94,8 +94,6 @@ link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
lower_packing_builtins(ir, lower_inst); lower_packing_builtins(ir, lower_inst);
} }
if (!pscreen->get_param(pscreen, PIPE_CAP_TEXTURE_GATHER_OFFSETS))
lower_offset_arrays(ir);
do_mat_op_to_vec(ir); do_mat_op_to_vec(ir);
if (stage == MESA_SHADER_FRAGMENT && pscreen->get_param(pscreen, PIPE_CAP_FBFETCH)) if (stage == MESA_SHADER_FRAGMENT && pscreen->get_param(pscreen, PIPE_CAP_FBFETCH))

9
src/mesa/state_tracker/st_glsl_to_nir.cpp
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@@ -1029,10 +1029,13 @@ st_finalize_nir(struct st_context *st, struct gl_program *prog,
NIR_PASS_V(nir, nir_split_var_copies); NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_lower_var_copies); NIR_PASS_V(nir, nir_lower_var_copies);
if (st->lower_rect_tex) { const bool lower_tg4_offsets =
struct nir_lower_tex_options opts = { 0 }; !st->screen->get_param(screen, PIPE_CAP_TEXTURE_GATHER_OFFSETS);
opts.lower_rect = true; if (st->lower_rect_tex || lower_tg4_offsets) {
struct nir_lower_tex_options opts = {0};
opts.lower_rect = !!st->lower_rect_tex;
opts.lower_tg4_offsets = lower_tg4_offsets;
NIR_PASS_V(nir, nir_lower_tex, &opts); NIR_PASS_V(nir, nir_lower_tex, &opts);
} }