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radv,aco: export legacy vertex outputs in NIR

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This new behaviour will let us insert exports in GS copy shader control
flow.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>
This commit is contained in:
Rhys Perry
2022-09-27 19:26:11 +01:00
committed by Marge Bot
parent 09eb2a4023
commit 19d0403594
4 changed files with 11 additions and 76 deletions
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24
src/amd/vulkan/radv_nir_to_llvm.c
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@@ -1161,15 +1161,9 @@ handle_shader_outputs_post(struct ac_shader_abi *abi)
switch (ctx->stage) {
case MESA_SHADER_VERTEX:
if (ctx->shader_info->vs.as_ls)
break; /* Lowered in NIR */
else if (ctx->shader_info->vs.as_es)
break; /* Lowered in NIR */
else if (ctx->shader_info->is_ngg)
break; /* Lowered in NIR */
else
handle_vs_outputs_post(ctx);
break;
case MESA_SHADER_TESS_CTRL:
case MESA_SHADER_TESS_EVAL:
break; /* Lowered in NIR */
case MESA_SHADER_FRAGMENT:
handle_fs_outputs_post(ctx);
break;
@@ -1179,16 +1173,6 @@ handle_shader_outputs_post(struct ac_shader_abi *abi)
else
emit_gs_epilogue(ctx);
break;
case MESA_SHADER_TESS_CTRL:
break; /* Lowered in NIR */
case MESA_SHADER_TESS_EVAL:
if (ctx->shader_info->tes.as_es)
break; /* Lowered in NIR */
else if (ctx->shader_info->is_ngg)
break; /* Lowered in NIR */
else
handle_vs_outputs_post(ctx);
break;
default:
break;
}
@@ -1462,7 +1446,9 @@ ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
ctx.abi.emit_vertex_with_counter = visit_emit_vertex_with_counter;
ctx.abi.emit_primitive = visit_end_primitive;
} else if (shaders[shader_idx]->info.stage == MESA_SHADER_TESS_EVAL) {
ctx.abi.export_vertex = radv_llvm_visit_export_vertex;
} else if (shaders[shader_idx]->info.stage == MESA_SHADER_VERTEX) {
ctx.abi.export_vertex = radv_llvm_visit_export_vertex;
ctx.abi.load_inputs = radv_load_vs_inputs;
}