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radv: Move radv_nir_* to a new folder.

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Also ran clang-format on the affected code.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21971>
This commit is contained in:
Timur Kristóf
2023-03-28 22:13:23 +02:00
committed by Marge Bot
parent dd8d52cabc
commit 1978eaf5b2
9 changed files with 114 additions and 54 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/amd/vulkan/meson.build
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@@ -70,6 +70,11 @@ libradv_files = files(
'meta/radv_meta_resolve.c',
'meta/radv_meta_resolve_cs.c',
'meta/radv_meta_resolve_fs.c',
'nir/radv_nir.h',
'nir/radv_nir_apply_pipeline_layout.c',
'nir/radv_nir_lower_abi.c',
'nir/radv_nir_lower_ray_queries.c',
'nir/radv_nir_lower_vs_inputs.c',
'winsys/null/radv_null_bo.c',
'winsys/null/radv_null_bo.h',
'winsys/null/radv_null_cs.c',
@@ -93,10 +98,6 @@ libradv_files = files(
'radv_formats.c',
'radv_image.c',
'radv_instance.c',
'radv_nir_apply_pipeline_layout.c',
'radv_nir_lower_abi.c',
'radv_nir_lower_ray_queries.c',
'radv_nir_lower_vs_inputs.c',
'radv_perfcounter.c',
'radv_physical_device.c',
'radv_pipeline.c',

64
src/amd/vulkan/nir/radv_nir.h Normal file
View File

@@ -0,0 +1,64 @@
/*
* Copyright © 2023 Valve Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#ifndef RADV_NIR_H
#define RADV_NIR_H
#include <stdbool.h>
#include <stdint.h>
#include "amd_family.h"
#include "nir.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct nir_shader nir_shader;
struct radeon_info;
struct radv_pipeline_layout;
struct radv_pipeline_key;
struct radv_pipeline_stage;
struct radv_shader_info;
struct radv_shader_args;
struct radv_device;
void radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device,
const struct radv_pipeline_layout *layout,
const struct radv_shader_info *info,
const struct radv_shader_args *args);
void radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level,
const struct radv_shader_info *info, const struct radv_shader_args *args,
const struct radv_pipeline_key *pl_key, uint32_t address32_hi);
bool radv_nir_lower_ray_queries(struct nir_shader *shader, struct radv_device *device);
bool radv_nir_lower_vs_inputs(nir_shader *shader, const struct radv_pipeline_stage *vs_stage,
const struct radv_pipeline_key *pl_key,
const struct radeon_info *rad_info);
#ifdef __cplusplus
}
#endif
#endif /* RADV_NIR_H */

14
src/amd/vulkan/radv_nir_apply_pipeline_layout.c → src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c
View File

@@ -24,6 +24,7 @@
#include "ac_shader_util.h"
#include "nir.h"
#include "nir_builder.h"
#include "radv_nir.h"
#include "radv_private.h"
#include "radv_shader.h"
#include "radv_shader_args.h"
@@ -141,10 +142,10 @@ static void
visit_load_vulkan_descriptor(nir_builder *b, apply_layout_state *state, nir_intrinsic_instr *intrin)
{
if (nir_intrinsic_desc_type(intrin) == VK_DESCRIPTOR_TYPE_ACCELERATION_STRUCTURE_KHR) {
nir_ssa_def *addr = convert_pointer_to_64_bit(
b, state,
nir_iadd(b, nir_unpack_64_2x32_split_x(b, intrin->src[0].ssa),
nir_unpack_64_2x32_split_y(b, intrin->src[0].ssa)));
nir_ssa_def *addr =
convert_pointer_to_64_bit(b, state,
nir_iadd(b, nir_unpack_64_2x32_split_x(b, intrin->src[0].ssa),
nir_unpack_64_2x32_split_y(b, intrin->src[0].ssa)));
nir_ssa_def *desc = nir_build_load_global(b, 1, 64, addr, .access = ACCESS_NON_WRITEABLE);
nir_ssa_def_rewrite_uses(&intrin->dest.ssa, desc);
@@ -258,8 +259,9 @@ get_sampler_desc(nir_builder *b, apply_layout_state *state, nir_deref_instr *der
uint32_t dword0_mask = tex->op == nir_texop_tg4 ? C_008F30_TRUNC_COORD : 0xffffffffu;
const uint32_t *samplers = radv_immutable_samplers(layout, binding);
return nir_imm_ivec4(b, samplers[constant_index * 4 + 0] & dword0_mask, samplers[constant_index * 4 + 1],
samplers[constant_index * 4 + 2], samplers[constant_index * 4 + 3]);
return nir_imm_ivec4(b, samplers[constant_index * 4 + 0] & dword0_mask,
samplers[constant_index * 4 + 1], samplers[constant_index * 4 + 2],
samplers[constant_index * 4 + 3]);
}
unsigned size = 8;

56
src/amd/vulkan/radv_nir_lower_abi.c → src/amd/vulkan/nir/radv_nir_lower_abi.c
View File

@@ -21,10 +21,11 @@
* IN THE SOFTWARE.
*/
#include "ac_nir.h"
#include "nir.h"
#include "nir_builder.h"
#include "ac_nir.h"
#include "radv_constants.h"
#include "radv_nir.h"
#include "radv_private.h"
#include "radv_shader.h"
#include "radv_shader_args.h"
@@ -41,13 +42,12 @@ typedef struct {
static nir_ssa_def *
load_ring(nir_builder *b, unsigned ring, lower_abi_state *s)
{
struct ac_arg arg =
b->shader->info.stage == MESA_SHADER_TASK ?
s->args->task_ring_offsets :
s->args->ac.ring_offsets;
struct ac_arg arg = b->shader->info.stage == MESA_SHADER_TASK ? s->args->task_ring_offsets
: s->args->ac.ring_offsets;
nir_ssa_def *ring_offsets = ac_nir_load_arg(b, &s->args->ac, arg);
ring_offsets = nir_pack_64_2x32_split(b, nir_channel(b, ring_offsets, 0), nir_channel(b, ring_offsets, 1));
ring_offsets =
nir_pack_64_2x32_split(b, nir_channel(b, ring_offsets, 0), nir_channel(b, ring_offsets, 1));
return nir_load_smem_amd(b, 4, ring_offsets, nir_imm_int(b, ring * 16u), .align_mul = 4u);
}
@@ -136,8 +136,9 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
case nir_intrinsic_load_ring_attr_offset_amd: {
nir_ssa_def *ring_attr_offset = ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_attr_offset);
replacement = nir_ishl(b, nir_ubfe(b, ring_attr_offset, nir_imm_int(b, 0), nir_imm_int(b, 15)),
nir_imm_int(b, 9)); /* 512b increments. */
replacement =
nir_ishl(b, nir_ubfe(b, ring_attr_offset, nir_imm_int(b, 0), nir_imm_int(b, 15)),
nir_imm_int(b, 9)); /* 512b increments. */
break;
}
@@ -152,7 +153,8 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
*/
nir_ssa_def *arg = ac_nir_load_arg(b, &s->args->ac, s->args->ac.tes_rel_patch_id);
nir_intrinsic_instr *load_arg = nir_instr_as_intrinsic(arg->parent_instr);
nir_intrinsic_set_arg_upper_bound_u32_amd(load_arg, 2048 / MAX2(b->shader->info.tess.tcs_vertices_out, 1));
nir_intrinsic_set_arg_upper_bound_u32_amd(
load_arg, 2048 / MAX2(b->shader->info.tess.tcs_vertices_out, 1));
replacement = arg;
} else {
unreachable("invalid tessellation shader stage");
@@ -168,8 +170,7 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
}
} else if (stage == MESA_SHADER_TESS_EVAL) {
replacement = nir_imm_int(b, b->shader->info.tess.tcs_vertices_out);
}
else
} else
unreachable("invalid tessellation shader stage");
break;
case nir_intrinsic_load_gs_vertex_offset_amd:
@@ -185,7 +186,8 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
nir_imm_int(b, 22), nir_imm_int(b, 9));
break;
case nir_intrinsic_load_packed_passthrough_primitive_amd:
/* NGG passthrough mode: the HW already packs the primitive export value to a single register. */
/* NGG passthrough mode: the HW already packs the primitive export value to a single register.
*/
replacement = ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_vtx_offset[0]);
break;
case nir_intrinsic_load_pipeline_stat_query_enabled_amd:
@@ -273,9 +275,8 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
replacement = ac_nir_load_arg(b, &s->args->ac, s->args->ac.task_ring_entry);
break;
case nir_intrinsic_load_lshs_vertex_stride_amd: {
unsigned io_num = stage == MESA_SHADER_VERTEX ?
s->info->vs.num_linked_outputs :
s->info->tcs.num_linked_inputs;
unsigned io_num = stage == MESA_SHADER_VERTEX ? s->info->vs.num_linked_outputs
: s->info->tcs.num_linked_inputs;
replacement = nir_imm_int(b, io_num * 16);
break;
}
@@ -289,8 +290,8 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
}
case nir_intrinsic_load_hs_out_patch_data_offset_amd: {
unsigned out_vertices_per_patch = b->shader->info.tess.tcs_vertices_out;
unsigned num_tcs_outputs = stage == MESA_SHADER_TESS_CTRL ?
s->info->tcs.num_linked_outputs : s->info->tes.num_linked_inputs;
unsigned num_tcs_outputs = stage == MESA_SHADER_TESS_CTRL ? s->info->tcs.num_linked_outputs
: s->info->tes.num_linked_inputs;
int per_vertex_output_patch_size = out_vertices_per_patch * num_tcs_outputs * 16u;
if (s->pl_key->dynamic_patch_control_points) {
@@ -324,8 +325,8 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
offset = nir_iadd(b, offset, nir_ishl_imm(b, intrin->src[1].ssa, 3));
}
replacement = nir_load_global_amd(b, 2, 32, addr, offset,
.base = sample_pos_offset, .access = ACCESS_NON_WRITEABLE);
replacement = nir_load_global_amd(b, 2, 32, addr, offset, .base = sample_pos_offset,
.access = ACCESS_NON_WRITEABLE);
break;
}
case nir_intrinsic_load_rasterization_samples_amd:
@@ -363,14 +364,16 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
nir_imm_int(b, 0x100));
break;
case nir_intrinsic_atomic_add_gen_prim_count_amd:
nir_gds_atomic_add_amd(b, 32, intrin->src[0].ssa,
nir_imm_int(b, RADV_NGG_QUERY_PRIM_GEN_OFFSET(nir_intrinsic_stream_id(intrin))),
nir_imm_int(b, 0x100));
nir_gds_atomic_add_amd(
b, 32, intrin->src[0].ssa,
nir_imm_int(b, RADV_NGG_QUERY_PRIM_GEN_OFFSET(nir_intrinsic_stream_id(intrin))),
nir_imm_int(b, 0x100));
break;
case nir_intrinsic_atomic_add_xfb_prim_count_amd:
nir_gds_atomic_add_amd(b, 32, intrin->src[0].ssa,
nir_imm_int(b, RADV_NGG_QUERY_PRIM_XFB_OFFSET(nir_intrinsic_stream_id(intrin))),
nir_imm_int(b, 0x100));
nir_gds_atomic_add_amd(
b, 32, intrin->src[0].ssa,
nir_imm_int(b, RADV_NGG_QUERY_PRIM_XFB_OFFSET(nir_intrinsic_stream_id(intrin))),
nir_imm_int(b, 0x100));
break;
case nir_intrinsic_atomic_add_gs_invocation_count_amd:
/* TODO: add gs invocation query emulation. */
@@ -440,7 +443,8 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
break;
}
case nir_intrinsic_load_ordered_id_amd:
replacement = nir_ubfe_imm(b, ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_tg_info), 0, 12);
replacement =
nir_ubfe_imm(b, ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_tg_info), 0, 12);
break;
case nir_intrinsic_load_force_vrs_rates_amd:
replacement = ac_nir_load_arg(b, &s->args->ac, s->args->ac.force_vrs_rates);

1
src/amd/vulkan/radv_nir_lower_ray_queries.c → src/amd/vulkan/nir/radv_nir_lower_ray_queries.c
View File

@@ -27,6 +27,7 @@
#include "util/hash_table.h"
#include "bvh/bvh.h"
#include "radv_nir.h"
#include "radv_private.h"
#include "radv_rt_common.h"
#include "radv_shader.h"

1
src/amd/vulkan/radv_nir_lower_vs_inputs.c → src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c
View File

@@ -25,6 +25,7 @@
#include "nir.h"
#include "nir_builder.h"
#include "radv_constants.h"
#include "radv_nir.h"
#include "radv_private.h"
#include "radv_shader.h"
#include "radv_shader_args.h"

3
src/amd/vulkan/radv_pipeline.c
View File

@@ -25,9 +25,11 @@
* IN THE SOFTWARE.
*/
#include "meta/radv_meta.h"
#include "nir/nir.h"
#include "nir/nir_builder.h"
#include "nir/nir_vulkan.h"
#include "nir/radv_nir.h"
#include "spirv/nir_spirv.h"
#include "util/disk_cache.h"
#include "util/mesa-sha1.h"
@@ -35,7 +37,6 @@
#include "util/u_atomic.h"
#include "radv_cs.h"
#include "radv_debug.h"
#include "meta/radv_meta.h"
#include "radv_private.h"
#include "radv_shader.h"
#include "radv_shader_args.h"

5
src/amd/vulkan/radv_shader.c
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@@ -26,17 +26,18 @@
*/
#include "radv_shader.h"
#include "meta/radv_meta.h"
#include "nir/nir.h"
#include "nir/nir_builder.h"
#include "nir/nir_xfb_info.h"
#include "nir/radv_nir.h"
#include "spirv/nir_spirv.h"
#include "util/memstream.h"
#include "util/mesa-sha1.h"
#include "util/u_atomic.h"
#include "util/streaming-load-memcpy.h"
#include "util/u_atomic.h"
#include "radv_cs.h"
#include "radv_debug.h"
#include "meta/radv_meta.h"
#include "radv_private.h"
#include "radv_shader_args.h"

15
src/amd/vulkan/radv_shader.h
View File

@@ -551,13 +551,6 @@ struct radv_pipeline_stage;
void radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively);
void radv_optimize_nir_algebraic(nir_shader *shader, bool opt_offsets);
bool radv_nir_lower_ray_queries(nir_shader *shader, struct radv_device *device);
void radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device,
const struct radv_pipeline_layout *layout,
const struct radv_shader_info *info,
const struct radv_shader_args *args);
void radv_postprocess_nir(struct radv_device *device,
const struct radv_pipeline_layout *pipeline_layout,
const struct radv_pipeline_key *pipeline_key, unsigned last_vgt_api_stage,
@@ -570,14 +563,6 @@ nir_shader *radv_shader_spirv_to_nir(struct radv_device *device,
const struct radv_pipeline_key *key,
bool is_internal);
void radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level,
const struct radv_shader_info *info, const struct radv_shader_args *args,
const struct radv_pipeline_key *pl_key, uint32_t address32_hi);
bool radv_nir_lower_vs_inputs(nir_shader *shader, const struct radv_pipeline_stage *vs_stage,
const struct radv_pipeline_key *key,
const struct radeon_info *rad_info);
void radv_init_shader_arenas(struct radv_device *device);
void radv_destroy_shader_arenas(struct radv_device *device);
VkResult radv_init_shader_upload_queue(struct radv_device *device);