From 1846eed38b25bd1aee650ab53c6e408364654b1d Mon Sep 17 00:00:00 2001
From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Fri, 19 Jul 2024 13:24:11 +0200
Subject: [PATCH] radv/meta: create the layout for clear depth/stencil
 on-demand

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30262>
---
 src/amd/vulkan/meta/radv_meta_clear.c | 55 +++++++++++++++------------
 1 file changed, 30 insertions(+), 25 deletions(-)

diff --git a/src/amd/vulkan/meta/radv_meta_clear.c b/src/amd/vulkan/meta/radv_meta_clear.c
index ffba76b691c..b6c6da7d537 100644
--- a/src/amd/vulkan/meta/radv_meta_clear.c
+++ b/src/amd/vulkan/meta/radv_meta_clear.c
@@ -417,6 +417,30 @@ create_depthstencil_pipeline(struct radv_device *device, VkImageAspectFlags aspe
    struct nir_shader *vs_nir, *fs_nir;
    VkResult result;
 
+   if (!device->meta_state.clear_depth_p_layout) {
+      const VkPushConstantRange pc_range_depth = {
+         .stageFlags = VK_SHADER_STAGE_VERTEX_BIT,
+         .size = 4,
+      };
+
+      result =
+         radv_meta_create_pipeline_layout(device, NULL, 1, &pc_range_depth, &device->meta_state.clear_depth_p_layout);
+      if (result != VK_SUCCESS)
+         return result;
+   }
+
+   if (!device->meta_state.clear_depth_unrestricted_p_layout) {
+      const VkPushConstantRange pc_range_depth_unrestricted = {
+         .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
+         .size = 4,
+      };
+
+      result = radv_meta_create_pipeline_layout(device, NULL, 1, &pc_range_depth_unrestricted,
+                                                &device->meta_state.clear_depth_unrestricted_p_layout);
+      if (result != VK_SUCCESS)
+         return result;
+   }
+
    build_depthstencil_shader(device, &vs_nir, &fs_nir, unrestricted);
 
    const VkPipelineVertexInputStateCreateInfo vi_state = {
@@ -548,6 +572,12 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer, VkClearDepthStencilV
    assert(util_is_power_of_two_nonzero(samples));
    samples_log2 = ffs(samples) - 1;
 
+   result = get_depth_stencil_pipeline(device, samples_log2, aspects, can_fast_clear, &pipeline);
+   if (result != VK_SUCCESS) {
+      vk_command_buffer_set_error(&cmd_buffer->vk, result);
+      return;
+   }
+
    if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
       clear_value.depth = 1.0f;
 
@@ -565,12 +595,6 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer, VkClearDepthStencilV
       radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT, clear_value.stencil);
    }
 
-   result = get_depth_stencil_pipeline(device, samples_log2, aspects, can_fast_clear, &pipeline);
-   if (result != VK_SUCCESS) {
-      vk_command_buffer_set_error(&cmd_buffer->vk, result);
-      return;
-   }
-
    radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
 
    if (can_fast_clear)
@@ -1009,25 +1033,6 @@ radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
    VkResult res;
    struct radv_meta_state *state = &device->meta_state;
 
-   const VkPushConstantRange pc_range_depth = {
-      .stageFlags = VK_SHADER_STAGE_VERTEX_BIT,
-      .size = 4,
-   };
-
-   res = radv_meta_create_pipeline_layout(device, NULL, 1, &pc_range_depth, &device->meta_state.clear_depth_p_layout);
-   if (res != VK_SUCCESS)
-      return res;
-
-   const VkPushConstantRange pc_range_depth_unrestricted = {
-      .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
-      .size = 4,
-   };
-
-   res = radv_meta_create_pipeline_layout(device, NULL, 1, &pc_range_depth_unrestricted,
-                                          &device->meta_state.clear_depth_unrestricted_p_layout);
-   if (res != VK_SUCCESS)
-      return res;
-
    res = init_meta_clear_dcc_comp_to_single_state(device, on_demand);
    if (res != VK_SUCCESS)
       return res;