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nir: Remove reg_intrinsics parameter to convert_from_ssa

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24450>
This commit is contained in:
Alyssa Rosenzweig
2023-08-01 10:35:21 -04:00
parent 11a161b9b9
commit 17d66055ae
14 changed files with 21 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/broadcom/compiler/vir.c
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@@ -1635,7 +1635,7 @@ v3d_attempt_compile(struct v3d_compile *c)
NIR_PASS(_, c->s, nir_lower_bool_to_int32);
NIR_PASS(_, c->s, nir_convert_to_lcssa, true, true);
NIR_PASS_V(c->s, nir_divergence_analysis);
NIR_PASS(_, c->s, nir_convert_from_ssa, true, true);
NIR_PASS(_, c->s, nir_convert_from_ssa, true);
struct nir_schedule_options schedule_options = {
/* Schedule for about half our register space, to enable more

6
src/compiler/nir/nir.h
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@@ -5992,12 +5992,10 @@ nir_rewrite_uses_to_load_reg(struct nir_builder *b, nir_ssa_def *old,
/* If phi_webs_only is true, only convert SSA values involved in phi nodes to
* registers. If false, convert all values (even those not involved in a phi
* node) to registers. If reg_intrinsics is true, it will use
* decl/load/store_reg intrinsics instead of nir_register.
* node) to registers.
*/
bool nir_convert_from_ssa(nir_shader *shader,
bool phi_webs_only,
bool reg_intrinsics);
bool phi_webs_only);
bool nir_lower_phis_to_regs_block(nir_block *block);
bool nir_lower_ssa_defs_to_regs_block(nir_block *block);

13
src/compiler/nir/nir_from_ssa.c
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@@ -1334,8 +1334,7 @@ resolve_parallel_copies_block(nir_block *block, struct from_ssa_state *state)
static bool
nir_convert_from_ssa_impl(nir_function_impl *impl,
bool phi_webs_only,
bool reg_intrinsics)
bool phi_webs_only)
{
nir_shader *shader = impl->function->shader;
@@ -1344,7 +1343,7 @@ nir_convert_from_ssa_impl(nir_function_impl *impl,
state.builder = nir_builder_create(impl);
state.dead_ctx = ralloc_context(NULL);
state.phi_webs_only = phi_webs_only;
state.reg_intrinsics = reg_intrinsics;
state.reg_intrinsics = true;
state.merge_node_table = _mesa_pointer_hash_table_create(NULL);
state.progress = false;
exec_list_make_empty(&state.dead_instrs);
@@ -1374,7 +1373,7 @@ nir_convert_from_ssa_impl(nir_function_impl *impl,
aggressive_coalesce_block(block, &state);
}
if (reg_intrinsics) {
if (state.reg_intrinsics) {
resolve_registers_impl(impl, &state);
} else {
nir_foreach_block(block, impl) {
@@ -1398,14 +1397,12 @@ nir_convert_from_ssa_impl(nir_function_impl *impl,
bool
nir_convert_from_ssa(nir_shader *shader,
bool phi_webs_only,
bool reg_intrinsics)
bool phi_webs_only)
{
bool progress = false;
nir_foreach_function_impl(impl, shader) {
progress |= nir_convert_from_ssa_impl(impl, phi_webs_only,
reg_intrinsics);
progress |= nir_convert_from_ssa_impl(impl, phi_webs_only);
}
return progress;

2
src/gallium/auxiliary/gallivm/lp_bld_nir.c
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@@ -2896,7 +2896,7 @@ bool lp_build_nir_llvm(struct lp_build_nir_context *bld_base,
{
struct nir_function *func;
NIR_PASS_V(nir, nir_convert_from_ssa, true, true);
NIR_PASS_V(nir, nir_convert_from_ssa, true);
NIR_PASS_V(nir, nir_lower_locals_to_regs, 32);
NIR_PASS_V(nir, nir_remove_dead_derefs);
NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);

2
src/gallium/auxiliary/nir/nir_to_tgsi.c
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@@ -3972,7 +3972,7 @@ const void *nir_to_tgsi_options(struct nir_shader *s,
NIR_PASS_V(s, nir_opt_move, move_all);
NIR_PASS_V(s, nir_convert_from_ssa, true, true);
NIR_PASS_V(s, nir_convert_from_ssa, true);
NIR_PASS_V(s, nir_lower_vec_to_regs, ntt_vec_to_mov_writemask_cb, NULL);
/* locals_to_reg_intrinsics will leave dead derefs that are good to clean up.

2
src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c
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@@ -1042,7 +1042,7 @@ emit_shader(struct etna_compile *c, unsigned *num_temps, unsigned *num_consts)
}
/* call directly to avoid validation (load_const don't pass validation at this point) */
nir_convert_from_ssa(shader, true, true);
nir_convert_from_ssa(shader, true);
nir_trivialize_registers(shader);
etna_ra_assign(c, shader);

2
src/gallium/drivers/freedreno/a2xx/ir2_nir.c
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@@ -1154,7 +1154,7 @@ ir2_nir_compile(struct ir2_context *ctx, bool binning)
OPT_V(ctx->nir, nir_opt_algebraic_late);
OPT_V(ctx->nir, nir_lower_alu_to_scalar, ir2_alu_to_scalar_filter_cb, NULL);
OPT_V(ctx->nir, nir_convert_from_ssa, true, true);
OPT_V(ctx->nir, nir_convert_from_ssa, true);
OPT_V(ctx->nir, nir_move_vec_src_uses_to_dest);
OPT_V(ctx->nir, nir_lower_vec_to_regs, NULL, NULL);

4
src/gallium/drivers/lima/lima_program.c
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@@ -153,7 +153,7 @@ lima_program_optimize_vs_nir(struct nir_shader *s)
NIR_PASS_V(s, nir_copy_prop);
NIR_PASS_V(s, nir_opt_dce);
NIR_PASS_V(s, lima_nir_split_loads);
NIR_PASS_V(s, nir_convert_from_ssa, true, true);
NIR_PASS_V(s, nir_convert_from_ssa, true);
NIR_PASS_V(s, nir_opt_dce);
NIR_PASS_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
nir_sweep(s);
@@ -269,7 +269,7 @@ lima_program_optimize_fs_nir(struct nir_shader *s,
NIR_PASS_V(s, nir_copy_prop);
NIR_PASS_V(s, nir_opt_dce);
NIR_PASS_V(s, nir_convert_from_ssa, true, true);
NIR_PASS_V(s, nir_convert_from_ssa, true);
NIR_PASS_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
NIR_PASS_V(s, nir_move_vec_src_uses_to_dest);

2
src/gallium/drivers/r600/sfn/sfn_nir.cpp
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@@ -935,7 +935,7 @@ r600_shader_from_nir(struct r600_context *rctx,
NIR_PASS_V(sh, nir_lower_bool_to_int32);
NIR_PASS_V(sh, nir_lower_locals_to_regs, 32);
NIR_PASS_V(sh, nir_convert_from_ssa, true, true);
NIR_PASS_V(sh, nir_convert_from_ssa, true);
NIR_PASS_V(sh, nir_opt_dce);
if (rctx->screen->b.debug_flags & DBG_ALL_SHADERS) {

2
src/gallium/drivers/vc4/vc4_program.c
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@@ -2350,7 +2350,7 @@ vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
NIR_PASS_V(c->s, nir_lower_bool_to_int32);
NIR_PASS_V(c->s, nir_convert_from_ssa, true, true);
NIR_PASS_V(c->s, nir_convert_from_ssa, true);
NIR_PASS_V(c->s, nir_trivialize_registers);
if (VC4_DBG(NIR)) {

4
src/gallium/drivers/zink/zink_compiler.c
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@@ -3485,7 +3485,7 @@ compile_module(struct zink_screen *screen, struct zink_shader *zs, nir_shader *n
struct zink_shader_info *sinfo = &zs->sinfo;
prune_io(nir);
NIR_PASS_V(nir, nir_convert_from_ssa, true, true);
NIR_PASS_V(nir, nir_convert_from_ssa, true);
struct zink_shader_object obj;
struct spirv_shader *spirv = nir_to_spirv(nir, sinfo, screen->spirv_version);
@@ -5265,7 +5265,7 @@ zink_shader_tcs_create(struct zink_screen *screen, nir_shader *tes, unsigned ver
optimize_nir(nir, NULL);
NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
NIR_PASS_V(nir, nir_convert_from_ssa, true, true);
NIR_PASS_V(nir, nir_convert_from_ssa, true);
*nir_ret = nir;
zink_shader_serialize_blob(nir, &ret->blob);

2
src/intel/compiler/brw_nir.c
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@@ -1723,7 +1723,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
nir_validate_ssa_dominance(nir, "before nir_convert_from_ssa");
OPT(nir_convert_from_ssa, true, true);
OPT(nir_convert_from_ssa, true);
if (!is_scalar) {
OPT(nir_move_vec_src_uses_to_dest);

2
src/nouveau/codegen/nv50_ir_from_nir.cpp
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@@ -3356,7 +3356,7 @@ Converter::run()
NIR_PASS_V(nir, nir_lower_bit_size, Converter::lowerBitSizeCB, this);
NIR_PASS_V(nir, nir_divergence_analysis);
NIR_PASS_V(nir, nir_convert_from_ssa, true, true);
NIR_PASS_V(nir, nir_convert_from_ssa, true);
// Garbage collect dead instructions
nir_sweep(nir);

2
src/panfrost/midgard/midgard_compile.c
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@@ -480,7 +480,7 @@ optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend)
NIR_PASS_V(nir, nir_opt_move, move_all);
/* Take us out of SSA */
NIR_PASS(progress, nir, nir_convert_from_ssa, true, true);
NIR_PASS(progress, nir, nir_convert_from_ssa, true);
/* We are a vector architecture; write combine where possible */
NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);