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radv: add support for dynamic logic op enable

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18882>
This commit is contained in:
Samuel Pitoiset
2022-05-31 11:29:07 +02:00
committed by Marge Bot
parent f22290949d
commit 17b9aa92b7
3 changed files with 35 additions and 5 deletions
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9
src/amd/vulkan/radv_pipeline.c
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@@ -993,7 +993,8 @@ radv_pipeline_out_of_order_rast(struct radv_graphics_pipeline *pipeline,
return false;
/* Be conservative if a logic operation is enabled with color buffers. */
if (colormask && state->cb && state->cb->logic_op_enable)
if (colormask &&
((pipeline->dynamic_states & RADV_DYNAMIC_LOGIC_OP_ENABLE) || state->cb->logic_op_enable))
return false;
/* Be conservative if an extended dynamic depth/stencil state is
@@ -1870,7 +1871,7 @@ radv_pipeline_init_dynamic_state(struct radv_graphics_pipeline *pipeline,
}
if (radv_pipeline_has_color_attachments(state->rp) && states & RADV_DYNAMIC_LOGIC_OP) {
if (state->cb->logic_op_enable) {
if ((pipeline->dynamic_states & RADV_DYNAMIC_LOGIC_OP_ENABLE) || state->cb->logic_op_enable) {
dynamic->logic_op = si_translate_blend_logic_op(state->cb->logic_op);
} else {
dynamic->logic_op = V_028808_ROP3_COPY;
@@ -1895,6 +1896,10 @@ radv_pipeline_init_dynamic_state(struct radv_graphics_pipeline *pipeline,
dynamic->tess_domain_origin = state->ts->domain_origin;
}
if (radv_pipeline_has_color_attachments(state->rp) && states & RADV_DYNAMIC_LOGIC_OP_ENABLE) {
dynamic->logic_op_enable = state->cb->logic_op_enable;
}
pipeline->dynamic_state.mask = states;
}