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radv: add support for dynamic logic op enable

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18882>
This commit is contained in:
Samuel Pitoiset
2022-05-31 11:29:07 +02:00
committed by Marge Bot
parent f22290949d
commit 17b9aa92b7
3 changed files with 35 additions and 5 deletions
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29
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -124,6 +124,7 @@ const struct radv_dynamic_state default_dynamic_state = {
.patch_control_points = 0,
.polygon_mode = 0,
.tess_domain_origin = VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT,
.logic_op_enable = 0u,
};
static void
@@ -261,6 +262,8 @@ radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer, const struct radv_dy
RADV_CMP_COPY(tess_domain_origin, RADV_DYNAMIC_TESS_DOMAIN_ORIGIN);
RADV_CMP_COPY(logic_op_enable, RADV_DYNAMIC_LOGIC_OP_ENABLE);
#undef RADV_CMP_COPY
cmd_buffer->state.dirty |= dest_mask;
@@ -1478,7 +1481,8 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
if (!cmd_buffer->state.emitted_graphics_pipeline ||
cmd_buffer->state.emitted_graphics_pipeline->cb_color_control != pipeline->cb_color_control)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP |
RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP_ENABLE;
if (!cmd_buffer->state.emitted_graphics_pipeline ||
cmd_buffer->state.emitted_graphics_pipeline->cb_target_mask != pipeline->cb_target_mask)
@@ -1883,7 +1887,15 @@ radv_emit_logic_op(struct radv_cmd_buffer *cmd_buffer)
unsigned cb_color_control = cmd_buffer->state.graphics_pipeline->cb_color_control;
struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
cb_color_control |= S_028808_ROP3(d->logic_op);
if (d->logic_op_enable) {
cb_color_control |= S_028808_ROP3(d->logic_op);
} else {
cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
}
if (cmd_buffer->device->physical_device->rad_info.has_rbplus) {
cb_color_control |= S_028808_DISABLE_DUAL_QUAD(d->logic_op_enable);
}
radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, cb_color_control);
}
@@ -3391,7 +3403,7 @@ radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer, bool pip
if (states & RADV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE)
radv_emit_rasterizer_discard_enable(cmd_buffer);
if (states & RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP)
if (states & (RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP | RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP_ENABLE))
radv_emit_logic_op(cmd_buffer);
if (states & RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE)
@@ -5822,6 +5834,17 @@ radv_CmdSetTessellationDomainOriginEXT(VkCommandBuffer commandBuffer,
state->dirty |= RADV_CMD_DIRTY_DYNAMIC_TESS_DOMAIN_ORIGIN;
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetLogicOpEnableEXT(VkCommandBuffer commandBuffer, VkBool32 logicOpEnable)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_cmd_state *state = &cmd_buffer->state;
state->dynamic.logic_op_enable = logicOpEnable;
state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP_ENABLE;
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount,
const VkCommandBuffer *pCmdBuffers)

9
src/amd/vulkan/radv_pipeline.c
View File

@@ -993,7 +993,8 @@ radv_pipeline_out_of_order_rast(struct radv_graphics_pipeline *pipeline,
return false;
/* Be conservative if a logic operation is enabled with color buffers. */
if (colormask && state->cb && state->cb->logic_op_enable)
if (colormask &&
((pipeline->dynamic_states & RADV_DYNAMIC_LOGIC_OP_ENABLE) || state->cb->logic_op_enable))
return false;
/* Be conservative if an extended dynamic depth/stencil state is
@@ -1870,7 +1871,7 @@ radv_pipeline_init_dynamic_state(struct radv_graphics_pipeline *pipeline,
}
if (radv_pipeline_has_color_attachments(state->rp) && states & RADV_DYNAMIC_LOGIC_OP) {
if (state->cb->logic_op_enable) {
if ((pipeline->dynamic_states & RADV_DYNAMIC_LOGIC_OP_ENABLE) || state->cb->logic_op_enable) {
dynamic->logic_op = si_translate_blend_logic_op(state->cb->logic_op);
} else {
dynamic->logic_op = V_028808_ROP3_COPY;
@@ -1895,6 +1896,10 @@ radv_pipeline_init_dynamic_state(struct radv_graphics_pipeline *pipeline,
dynamic->tess_domain_origin = state->ts->domain_origin;
}
if (radv_pipeline_has_color_attachments(state->rp) && states & RADV_DYNAMIC_LOGIC_OP_ENABLE) {
dynamic->logic_op_enable = state->cb->logic_op_enable;
}
pipeline->dynamic_state.mask = states;
}

2
src/amd/vulkan/radv_private.h
View File

@@ -1355,6 +1355,8 @@ struct radv_dynamic_state {
uint32_t polygon_mode;
VkTessellationDomainOrigin tess_domain_origin;
bool logic_op_enable;
};
extern const struct radv_dynamic_state default_dynamic_state;