OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel/brw: Move out of fs_visitor and rename print instructions

Browse Source 
They use the brw_print prefix now.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30169>
This commit is contained in:
Caio Oliveira
2024-07-12 16:32:36 -07:00
committed by Marge Bot
parent bb7f2db5a2
commit 17b7e49089
7 changed files with 39 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/intel/compiler/brw_cfg.cpp
View File

@@ -162,7 +162,7 @@ bblock_t::dump(FILE *file) const
int ip = this->start_ip;
foreach_inst_in_block(fs_inst, inst, this) {
fprintf(file, "%5d: ", ip);
s->dump_instruction(inst, file);
brw_print_instruction(*s, inst, file);
ip++;
}
}

2
src/intel/compiler/brw_fs.cpp
View File

@@ -1593,7 +1593,7 @@ fs_visitor::debug_optimizer(const nir_shader *nir,
iteration, pass_num, pass_name);
if (ret == -1)
return;
dump_instructions(filename);
brw_print_instructions(*this);
free(filename);
}

18
src/intel/compiler/brw_fs.h
View File

@@ -335,15 +335,6 @@ public:
brw_reg per_primitive_reg(const brw::fs_builder &bld,
int location, unsigned comp);
void dump_instruction_to_file(const fs_inst *inst, FILE *file, const brw::def_analysis *defs) const;
void dump_instructions_to_file(FILE *file) const;
/* Convenience functions based on the above. */
void dump_instruction(const fs_inst *inst, FILE *file = stderr, const brw::def_analysis *defs = nullptr) const {
dump_instruction_to_file(inst, file, defs);
}
void dump_instructions(const char *name = nullptr) const;
void calculate_cfg();
const struct brw_compiler *compiler;
@@ -482,6 +473,15 @@ public:
int iteration, int pass_num) const;
};
void brw_print_instruction_to_file(const fs_visitor &s, const fs_inst *inst, FILE *file, const brw::def_analysis *defs);
void brw_print_instructions_to_file(const fs_visitor &s, FILE *file);
/* Convenience functions based on the above. */
inline void brw_print_instruction(const fs_visitor &s, const fs_inst *inst, FILE *file = stderr, const brw::def_analysis *defs = nullptr) {
brw_print_instruction_to_file(s, inst, file, defs);
}
void brw_print_instructions(const fs_visitor &s, const char *name = nullptr);
void brw_print_swsb(FILE *f, const struct intel_device_info *devinfo, const tgl_swsb swsb);
/**

2
src/intel/compiler/brw_fs_reg_allocate.cpp
View File

@@ -1146,7 +1146,7 @@ fs_visitor::assign_regs(bool allow_spilling, bool spill_all)
bool success = alloc.assign_regs(allow_spilling, spill_all);
if (!success && allow_spilling) {
fail("no register to spill:\n");
dump_instructions(NULL);
brw_print_instructions(*this, NULL);
}
return success;
}

8
src/intel/compiler/brw_fs_validate.cpp
View File

@@ -35,7 +35,7 @@
if (!(assertion)) { \
fprintf(stderr, "ASSERT: Scalar %s validation failed!\n", \
_mesa_shader_stage_to_abbrev(s.stage)); \
s.dump_instruction(inst, stderr); \
brw_print_instruction(s, inst, stderr); \
fprintf(stderr, "%s:%d: '%s' failed\n", __FILE__, __LINE__, #assertion); \
abort(); \
} \
@@ -48,7 +48,7 @@
if (a != b) { \
fprintf(stderr, "ASSERT: Scalar %s validation failed!\n", \
_mesa_shader_stage_to_abbrev(s.stage)); \
s.dump_instruction(inst, stderr); \
brw_print_instruction(s, inst, stderr); \
fprintf(stderr, "%s:%d: A == B failed\n", __FILE__, __LINE__); \
fprintf(stderr, " A = %s = %u\n", #A, a); \
fprintf(stderr, " B = %s = %u\n", #B, b); \
@@ -63,7 +63,7 @@
if (a == b) { \
fprintf(stderr, "ASSERT: Scalar %s validation failed!\n", \
_mesa_shader_stage_to_abbrev(s.stage)); \
s.dump_instruction(inst, stderr); \
brw_print_instruction(s, inst, stderr); \
fprintf(stderr, "%s:%d: A != B failed\n", __FILE__, __LINE__); \
fprintf(stderr, " A = %s = %u\n", #A, a); \
fprintf(stderr, " B = %s = %u\n", #B, b); \
@@ -78,7 +78,7 @@
if (a > b) { \
fprintf(stderr, "ASSERT: Scalar %s validation failed!\n", \
_mesa_shader_stage_to_abbrev(s.stage)); \
s.dump_instruction(inst, stderr); \
brw_print_instruction(s, inst, stderr); \
fprintf(stderr, "%s:%d: A <= B failed\n", __FILE__, __LINE__); \
fprintf(stderr, " A = %s = %u\n", #A, a); \
fprintf(stderr, " B = %s = %u\n", #B, b); \

38
src/intel/compiler/brw_print.cpp
View File

@@ -12,16 +12,16 @@
using namespace brw;
void
fs_visitor::dump_instructions_to_file(FILE *file) const
brw_print_instructions_to_file(const fs_visitor &s, FILE *file)
{
if (cfg && grf_used == 0) {
const brw::def_analysis &defs = def_analysis.require();
if (s.cfg && s.grf_used == 0) {
const brw::def_analysis &defs = s.def_analysis.require();
const register_pressure *rp =
INTEL_DEBUG(DEBUG_REG_PRESSURE) ? &regpressure_analysis.require() : NULL;
INTEL_DEBUG(DEBUG_REG_PRESSURE) ? &s.regpressure_analysis.require() : NULL;
unsigned ip = 0, max_pressure = 0;
unsigned cf_count = 0;
foreach_block_and_inst(block, fs_inst, inst, cfg) {
foreach_block_and_inst(block, fs_inst, inst, s.cfg) {
if (inst->is_control_flow_end())
cf_count -= 1;
@@ -32,7 +32,7 @@ fs_visitor::dump_instructions_to_file(FILE *file) const
for (unsigned i = 0; i < cf_count; i++)
fprintf(file, " ");
dump_instruction(inst, file, &defs);
brw_print_instruction(s, inst, file, &defs);
ip++;
if (inst->is_control_flow_begin())
@@ -40,19 +40,19 @@ fs_visitor::dump_instructions_to_file(FILE *file) const
}
if (rp)
fprintf(file, "Maximum %3d registers live at once.\n", max_pressure);
} else if (cfg && exec_list_is_empty(&instructions)) {
foreach_block_and_inst(block, fs_inst, inst, cfg) {
dump_instruction(inst, file);
} else if (s.cfg && exec_list_is_empty(&s.instructions)) {
foreach_block_and_inst(block, fs_inst, inst, s.cfg) {
brw_print_instruction(s, inst, file);
}
} else {
foreach_in_list(fs_inst, inst, &instructions) {
dump_instruction(inst, file);
foreach_in_list(fs_inst, inst, &s.instructions) {
brw_print_instruction(s, inst, file);
}
}
}
void
fs_visitor::dump_instructions(const char *name) const
brw_print_instructions(const fs_visitor &s, const char *name)
{
FILE *file = stderr;
if (name && __normal_user()) {
@@ -61,7 +61,7 @@ fs_visitor::dump_instructions(const char *name) const
file = stderr;
}
dump_instructions_to_file(file);
brw_print_instructions_to_file(s, file);
if (file != stderr) {
fclose(file);
@@ -314,7 +314,7 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op)
void
fs_visitor::dump_instruction_to_file(const fs_inst *inst, FILE *file, const brw::def_analysis *defs) const
brw_print_instruction_to_file(const fs_visitor &s, const fs_inst *inst, FILE *file, const brw::def_analysis *defs)
{
if (inst->predicate) {
fprintf(file, "(%cf%d.%d) ",
@@ -323,7 +323,7 @@ fs_visitor::dump_instruction_to_file(const fs_inst *inst, FILE *file, const brw:
inst->flag_subreg % 2);
}
fprintf(file, "%s", brw_instruction_name(&compiler->isa, inst->opcode));
fprintf(file, "%s", brw_instruction_name(&s.compiler->isa, inst->opcode));
if (inst->saturate)
fprintf(file, ".sat");
if (inst->conditional_mod) {
@@ -401,7 +401,7 @@ fs_visitor::dump_instruction_to_file(const fs_inst *inst, FILE *file, const brw:
if (inst->dst.offset ||
(inst->dst.file == VGRF &&
alloc.sizes[inst->dst.nr] * REG_SIZE != inst->size_written)) {
s.alloc.sizes[inst->dst.nr] * REG_SIZE != inst->size_written)) {
const unsigned reg_size = (inst->dst.file == UNIFORM ? 4 : REG_SIZE);
fprintf(file, "+%d.%d", inst->dst.offset / reg_size,
inst->dst.offset % reg_size);
@@ -514,7 +514,7 @@ fs_visitor::dump_instruction_to_file(const fs_inst *inst, FILE *file, const brw:
fprintf(file, ".%d", inst->src[i].subnr / brw_type_size_bytes(inst->src[i].type));
} else if (inst->src[i].offset ||
(inst->src[i].file == VGRF &&
alloc.sizes[inst->src[i].nr] * REG_SIZE != inst->size_read(i))) {
s.alloc.sizes[inst->src[i].nr] * REG_SIZE != inst->size_read(i))) {
const unsigned reg_size = (inst->src[i].file == UNIFORM ? 4 : REG_SIZE);
fprintf(file, "+%d.%d", inst->src[i].offset / reg_size,
inst->src[i].offset % reg_size);
@@ -543,7 +543,7 @@ fs_visitor::dump_instruction_to_file(const fs_inst *inst, FILE *file, const brw:
if (inst->force_writemask_all)
fprintf(file, "NoMask ");
if (inst->exec_size != dispatch_width)
if (inst->exec_size != s.dispatch_width)
fprintf(file, "group%d ", inst->group);
if (inst->has_no_mask_send_params)
@@ -551,7 +551,7 @@ fs_visitor::dump_instruction_to_file(const fs_inst *inst, FILE *file, const brw:
if (inst->sched.pipe != TGL_PIPE_NONE) {
fprintf(file, "{ ");
brw_print_swsb(file, devinfo, inst->sched);
brw_print_swsb(file, s.devinfo, inst->sched);
fprintf(file, " } ");
}

8
src/intel/compiler/brw_schedule_instructions.cpp
View File

@@ -1503,7 +1503,7 @@ instruction_scheduler::schedule(schedule_node *chosen)
if (debug) {
fprintf(stderr, "clock %4d, scheduled: ", current.time);
s->dump_instruction(chosen->inst);
brw_print_instruction(*s, chosen->inst);
}
}
@@ -1523,7 +1523,7 @@ instruction_scheduler::update_children(schedule_node *chosen)
if (debug) {
fprintf(stderr, "\tchild %d, %d parents: ", i, child->n->tmp.parent_count);
s->dump_instruction(child->n->inst);
brw_print_instruction(*s, child->n->inst);
}
child->n->tmp.cand_generation = current.cand_generation;
@@ -1578,7 +1578,7 @@ instruction_scheduler::run(instruction_scheduler_mode mode)
if (debug && !post_reg_alloc) {
fprintf(stderr, "\nInstructions before scheduling (reg_alloc %d)\n",
post_reg_alloc);
s->dump_instructions();
brw_print_instructions(*s);
}
if (!post_reg_alloc) {
@@ -1601,7 +1601,7 @@ instruction_scheduler::run(instruction_scheduler_mode mode)
if (debug && !post_reg_alloc) {
fprintf(stderr, "\nInstructions after scheduling (reg_alloc %d)\n",
post_reg_alloc);
s->dump_instructions();
brw_print_instructions(*s);
}
}