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anv: Fix return of PAT index for compressed bos for discrete GPUs

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Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29950>
This commit is contained in:
José Roberto de Souza
2024-07-15 07:55:08 -07:00
committed by Marge Bot
parent ad96a99385
commit 178950bf9b
1 changed files with 5 additions and 3 deletions
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8
src/intel/vulkan/anv_device.c
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@@ -5695,6 +5695,9 @@ anv_device_get_pat_entry(struct anv_device *device,
if (alloc_flags & ANV_BO_ALLOC_IMPORTED)
return &device->info->pat.cached_coherent;
if (alloc_flags & ANV_BO_ALLOC_COMPRESSED)
return &device->info->pat.compressed;
/* PAT indexes has no actual effect in DG2 and DG1, smem caches will always
* be snopped by GPU and lmem will always be WC.
* This might change in future discrete platforms.
@@ -5705,9 +5708,8 @@ anv_device_get_pat_entry(struct anv_device *device,
return &device->info->pat.writecombining;
}
if (alloc_flags & ANV_BO_ALLOC_COMPRESSED)
return &device->info->pat.compressed;
else if ((alloc_flags & (ANV_BO_ALLOC_HOST_CACHED_COHERENT)) == ANV_BO_ALLOC_HOST_CACHED_COHERENT)
/* Integrated platforms handling only */
if ((alloc_flags & (ANV_BO_ALLOC_HOST_CACHED_COHERENT)) == ANV_BO_ALLOC_HOST_CACHED_COHERENT)
return &device->info->pat.cached_coherent;
else if (alloc_flags & (ANV_BO_ALLOC_EXTERNAL | ANV_BO_ALLOC_SCANOUT))
return &device->info->pat.scanout;