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iris: Move a HIZ_CCS_WT fast-clear flush higher up

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The next patch will be update the clear value. Move the stalling flush
to the top of fast_clear_depth() so that there are no users of the clear
value when it is replaced.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30520>
This commit is contained in:
Nanley Chery
2024-08-14 20:34:35 -04:00
committed by Marge Bot
parent d7b0d32c28
commit 16f9b8e92c
1 changed files with 21 additions and 21 deletions
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42
src/gallium/drivers/iris/iris_clear.c
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@@ -529,6 +529,27 @@ fast_clear_depth(struct iris_context *ice,
bool update_clear_depth = false;
if (res->aux.usage == ISL_AUX_USAGE_HIZ_CCS_WT) {
/* From Bspec 47010 (Depth Buffer Clear):
*
* Since the fast clear cycles to CCS are not cached in TileCache,
* any previous depth buffer writes to overlapping pixels must be
* flushed out of TileCache before a succeeding Depth Buffer Clear.
* This restriction only applies to Depth Buffer with write-thru
* enabled, since fast clears to CCS only occur for write-thru mode.
*
* There may have been a write to this depth buffer. Flush it from the
* tile cache just in case.
*
* Set CS stall bit to guarantee that the fast clear starts the execution
* after the tile cache flush completed.
*/
iris_emit_pipe_control_flush(batch, "hiz_ccs_wt: before fast clear",
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_TILE_CACHE_FLUSH);
}
/* If we're clearing to a new clear value, then we need to resolve any clear
* flags out of the HiZ buffer into the real depth buffer.
*/
@@ -586,27 +607,6 @@ fast_clear_depth(struct iris_context *ice,
}
}
if (res->aux.usage == ISL_AUX_USAGE_HIZ_CCS_WT) {
/* From Bspec 47010 (Depth Buffer Clear):
*
* Since the fast clear cycles to CCS are not cached in TileCache,
* any previous depth buffer writes to overlapping pixels must be
* flushed out of TileCache before a succeeding Depth Buffer Clear.
* This restriction only applies to Depth Buffer with write-thru
* enabled, since fast clears to CCS only occur for write-thru mode.
*
* There may have been a write to this depth buffer. Flush it from the
* tile cache just in case.
*
* Set CS stall bit to guarantee that the fast clear starts the execution
* after the tile cache flush completed.
*/
iris_emit_pipe_control_flush(batch, "hiz_ccs_wt: before fast clear",
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_TILE_CACHE_FLUSH);
}
for (unsigned l = 0; l < box->depth; l++) {
enum isl_aux_state aux_state =
iris_resource_get_aux_state(res, level, box->z + l);