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radv: Fix depth-only-with-discard when epilogs are used.

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For a depth-only-with-discard pipeline, spi_shader_col_format needs to be
fixed up to a single channel export, or otherwise discard will not work.

Since col_format can change depending on the dynamic state, precompute the
need for this workaround on pipeline creation and apply it when emitting
prolog states.

Fixes: eb07a11b8f ("radv: add support for compiling PS epilogs on-demand")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20704>
This commit is contained in:
Tatsuyuki Ishi
2023-01-14 18:30:32 +09:00
committed by Marge Bot
parent 7bed7d9475
commit 1617dac6c3
3 changed files with 14 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -1899,8 +1899,10 @@ radv_emit_ps_epilog_state(struct radv_cmd_buffer *cmd_buffer, struct radv_shader
if (cmd_buffer->state.emitted_ps_epilog == ps_epilog && !pipeline_is_dirty) if (cmd_buffer->state.emitted_ps_epilog == ps_epilog && !pipeline_is_dirty)
return; return;
radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, uint32_t col_format = ps_epilog->spi_shader_col_format;
ps_epilog->spi_shader_col_format); if (pipeline->need_null_export_workaround && !col_format)
col_format = V_028714_SPI_SHADER_32_R;
radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, col_format);
radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK,
ac_get_cb_shader_mask(ps_epilog->spi_shader_col_format)); ac_get_cb_shader_mask(ps_epilog->spi_shader_col_format));
@@ -8541,6 +8543,9 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r
} }
cmd_buffer->state.col_format_non_compacted = ps_epilog->spi_shader_col_format; cmd_buffer->state.col_format_non_compacted = ps_epilog->spi_shader_col_format;
if (cmd_buffer->state.graphics_pipeline->need_null_export_workaround &&
!cmd_buffer->state.col_format_non_compacted)
cmd_buffer->state.col_format_non_compacted = V_028714_SPI_SHADER_32_R;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RBPLUS; cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RBPLUS;
} }

12
src/amd/vulkan/radv_pipeline.c
View File

@@ -5232,12 +5232,12 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
* color and Z formats to SPI_SHADER_ZERO. The hw will skip export * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
* instructions if any are present. * instructions if any are present.
*/ */
if ((device->physical_device->rad_info.gfx_level <= GFX9 || ps->info.ps.can_discard) && pipeline->need_null_export_workaround =
!blend.spi_shader_col_format) { (device->physical_device->rad_info.gfx_level <= GFX9 || ps->info.ps.can_discard) &&
if (!ps->info.ps.writes_z && !ps->info.ps.writes_stencil && !ps->info.ps.writes_sample_mask) { !ps->info.ps.writes_z && !ps->info.ps.writes_stencil && !ps->info.ps.writes_sample_mask;
blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R; if (pipeline->need_null_export_workaround && !blend.spi_shader_col_format) {
pipeline->col_format_non_compacted = V_028714_SPI_SHADER_32_R; blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
} pipeline->col_format_non_compacted = V_028714_SPI_SHADER_32_R;
} }
if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && !radv_pipeline_has_ngg(pipeline)) { if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && !radv_pipeline_has_ngg(pipeline)) {

1
src/amd/vulkan/radv_private.h
View File

@@ -2086,6 +2086,7 @@ struct radv_graphics_pipeline {
bool mrt0_is_dual_src; bool mrt0_is_dual_src;
uint8_t need_src_alpha; uint8_t need_src_alpha;
bool need_null_export_workaround;
bool uses_drawid; bool uses_drawid;
bool uses_baseinstance; bool uses_baseinstance;