radv: merge gather_tess_info() with radv_fill_shader_info()
Shouldn't introduce any functional changes. The dependencies between stages might be improved with a new helper that will link shader_info. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18184>
This commit is contained in:
Samuel Pitoiset
committed by
Marge Bot
Marge Bot
parent
7b94ca287b
commit
15a7361ce9
@@ -3495,6 +3495,60 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
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}
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}
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}
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}
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if (stages[MESA_SHADER_TESS_CTRL].nir) {
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stages[MESA_SHADER_TESS_CTRL].info.tcs.tes_reads_tess_factors =
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!!(stages[MESA_SHADER_TESS_EVAL].nir->info.inputs_read &
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(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
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stages[MESA_SHADER_TESS_CTRL].info.tcs.tes_inputs_read =
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stages[MESA_SHADER_TESS_EVAL].nir->info.inputs_read;
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stages[MESA_SHADER_TESS_CTRL].info.tcs.tes_patch_inputs_read =
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stages[MESA_SHADER_TESS_EVAL].nir->info.patch_inputs_read;
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stages[MESA_SHADER_TESS_EVAL].info.num_tess_patches =
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stages[MESA_SHADER_TESS_CTRL].info.num_tess_patches;
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stages[MESA_SHADER_GEOMETRY].info.num_tess_patches =
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stages[MESA_SHADER_TESS_CTRL].info.num_tess_patches;
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if (!radv_use_llvm_for_stage(device, MESA_SHADER_VERTEX)) {
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/* When the number of TCS input and output vertices are the same (typically 3):
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* - There is an equal amount of LS and HS invocations
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* - In case of merged LSHS shaders, the LS and HS halves of the shader
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* always process the exact same vertex. We can use this knowledge to optimize them.
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*
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* We don't set tcs_in_out_eq if the float controls differ because that might
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* involve different float modes for the same block and our optimizer
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* doesn't handle a instruction dominating another with a different mode.
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*/
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stages[MESA_SHADER_VERTEX].info.vs.tcs_in_out_eq =
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device->physical_device->rad_info.gfx_level >= GFX9 &&
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pipeline_key->tcs.tess_input_vertices == stages[MESA_SHADER_TESS_CTRL].info.tcs.tcs_vertices_out &&
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stages[MESA_SHADER_VERTEX].nir->info.float_controls_execution_mode ==
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stages[MESA_SHADER_TESS_CTRL].nir->info.float_controls_execution_mode;
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if (stages[MESA_SHADER_VERTEX].info.vs.tcs_in_out_eq)
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stages[MESA_SHADER_VERTEX].info.vs.tcs_temp_only_input_mask =
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stages[MESA_SHADER_TESS_CTRL].nir->info.inputs_read &
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stages[MESA_SHADER_VERTEX].nir->info.outputs_written &
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~stages[MESA_SHADER_TESS_CTRL].nir->info.tess.tcs_cross_invocation_inputs_read &
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~stages[MESA_SHADER_TESS_CTRL].nir->info.inputs_read_indirectly &
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~stages[MESA_SHADER_VERTEX].nir->info.outputs_accessed_indirectly;
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/* Copy data to TCS so it can be accessed by the backend if they are merged. */
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stages[MESA_SHADER_TESS_CTRL].info.vs.tcs_in_out_eq =
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stages[MESA_SHADER_VERTEX].info.vs.tcs_in_out_eq;
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stages[MESA_SHADER_TESS_CTRL].info.vs.tcs_temp_only_input_mask =
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stages[MESA_SHADER_VERTEX].info.vs.tcs_temp_only_input_mask;
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}
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for (gl_shader_stage s = MESA_SHADER_VERTEX; s <= MESA_SHADER_TESS_CTRL; ++s) {
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stages[s].info.workgroup_size =
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ac_compute_lshs_workgroup_size(device->physical_device->rad_info.gfx_level, s,
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stages[MESA_SHADER_TESS_CTRL].info.num_tess_patches,
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pipeline_key->tcs.tess_input_vertices,
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stages[MESA_SHADER_TESS_CTRL].info.tcs.tcs_vertices_out);
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}
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}
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/* PS always operates without workgroups. */
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/* PS always operates without workgroups. */
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if (stages[MESA_SHADER_FRAGMENT].nir)
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if (stages[MESA_SHADER_FRAGMENT].nir)
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stages[MESA_SHADER_FRAGMENT].info.workgroup_size = stages[MESA_SHADER_FRAGMENT].info.wave_size;
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stages[MESA_SHADER_FRAGMENT].info.workgroup_size = stages[MESA_SHADER_FRAGMENT].info.wave_size;
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@@ -3579,77 +3633,6 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag
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}
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}
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}
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}
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static void
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gather_tess_info(struct radv_device *device, struct radv_pipeline_stage *stages,
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const struct radv_pipeline_key *pipeline_key)
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{
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unsigned tess_in_patch_size = pipeline_key->tcs.tess_input_vertices;
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unsigned tess_out_patch_size = stages[MESA_SHADER_TESS_CTRL].nir->info.tess.tcs_vertices_out;
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/* Number of tessellation patches per workgroup processed by the current pipeline. */
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unsigned num_patches = get_tcs_num_patches(
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tess_in_patch_size, tess_out_patch_size,
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stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_inputs,
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stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_outputs,
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stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_patch_outputs,
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device->physical_device->hs.tess_offchip_block_dw_size, device->physical_device->rad_info.gfx_level,
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device->physical_device->rad_info.family);
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/* LDS size used by VS+TCS for storing TCS inputs and outputs. */
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unsigned tcs_lds_size = calculate_tess_lds_size(
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device->physical_device->rad_info.gfx_level, tess_in_patch_size, tess_out_patch_size,
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stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_inputs, num_patches,
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stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_outputs,
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stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_patch_outputs);
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stages[MESA_SHADER_TESS_CTRL].info.num_tess_patches = num_patches;
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stages[MESA_SHADER_TESS_CTRL].info.tcs.num_lds_blocks = tcs_lds_size;
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stages[MESA_SHADER_TESS_CTRL].info.tcs.tes_reads_tess_factors =
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!!(stages[MESA_SHADER_TESS_EVAL].nir->info.inputs_read &
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(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
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stages[MESA_SHADER_TESS_CTRL].info.tcs.tes_inputs_read = stages[MESA_SHADER_TESS_EVAL].nir->info.inputs_read;
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stages[MESA_SHADER_TESS_CTRL].info.tcs.tes_patch_inputs_read =
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stages[MESA_SHADER_TESS_EVAL].nir->info.patch_inputs_read;
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stages[MESA_SHADER_TESS_EVAL].info.num_tess_patches = num_patches;
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stages[MESA_SHADER_GEOMETRY].info.num_tess_patches = num_patches;
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if (!radv_use_llvm_for_stage(device, MESA_SHADER_VERTEX)) {
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/* When the number of TCS input and output vertices are the same (typically 3):
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* - There is an equal amount of LS and HS invocations
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* - In case of merged LSHS shaders, the LS and HS halves of the shader
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* always process the exact same vertex. We can use this knowledge to optimize them.
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*
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* We don't set tcs_in_out_eq if the float controls differ because that might
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* involve different float modes for the same block and our optimizer
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* doesn't handle a instruction dominating another with a different mode.
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*/
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stages[MESA_SHADER_VERTEX].info.vs.tcs_in_out_eq =
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device->physical_device->rad_info.gfx_level >= GFX9 &&
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tess_in_patch_size == tess_out_patch_size &&
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stages[MESA_SHADER_VERTEX].nir->info.float_controls_execution_mode ==
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stages[MESA_SHADER_TESS_CTRL].nir->info.float_controls_execution_mode;
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if (stages[MESA_SHADER_VERTEX].info.vs.tcs_in_out_eq)
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stages[MESA_SHADER_VERTEX].info.vs.tcs_temp_only_input_mask =
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stages[MESA_SHADER_TESS_CTRL].nir->info.inputs_read &
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stages[MESA_SHADER_VERTEX].nir->info.outputs_written &
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~stages[MESA_SHADER_TESS_CTRL].nir->info.tess.tcs_cross_invocation_inputs_read &
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~stages[MESA_SHADER_TESS_CTRL].nir->info.inputs_read_indirectly &
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~stages[MESA_SHADER_VERTEX].nir->info.outputs_accessed_indirectly;
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/* Copy data to TCS so it can be accessed by the backend if they are merged. */
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stages[MESA_SHADER_TESS_CTRL].info.vs.tcs_in_out_eq = stages[MESA_SHADER_VERTEX].info.vs.tcs_in_out_eq;
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stages[MESA_SHADER_TESS_CTRL].info.vs.tcs_temp_only_input_mask =
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stages[MESA_SHADER_VERTEX].info.vs.tcs_temp_only_input_mask;
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}
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for (gl_shader_stage s = MESA_SHADER_VERTEX; s <= MESA_SHADER_TESS_CTRL; ++s)
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stages[s].info.workgroup_size =
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ac_compute_lshs_workgroup_size(device->physical_device->rad_info.gfx_level, s, num_patches,
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tess_in_patch_size, tess_out_patch_size);
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}
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static bool
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static bool
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mem_vectorize_callback(unsigned align_mul, unsigned align_offset, unsigned bit_size,
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mem_vectorize_callback(unsigned align_mul, unsigned align_offset, unsigned bit_size,
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unsigned num_components, nir_intrinsic_instr *low, nir_intrinsic_instr *high,
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unsigned num_components, nir_intrinsic_instr *low, nir_intrinsic_instr *high,
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@@ -4725,10 +4708,6 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
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}
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}
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}
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}
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if (stages[MESA_SHADER_TESS_CTRL].nir) {
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gather_tess_info(device, stages, pipeline_key);
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}
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if (stages[MESA_SHADER_VERTEX].nir) {
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if (stages[MESA_SHADER_VERTEX].nir) {
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NIR_PASS(_, stages[MESA_SHADER_VERTEX].nir, radv_lower_vs_input, pipeline_key);
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NIR_PASS(_, stages[MESA_SHADER_VERTEX].nir, radv_lower_vs_input, pipeline_key);
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}
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}
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@@ -659,6 +659,23 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n
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break;
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break;
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case MESA_SHADER_TESS_CTRL:
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case MESA_SHADER_TESS_CTRL:
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info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
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info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
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/* Number of tessellation patches per workgroup processed by the current pipeline. */
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info->num_tess_patches =
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get_tcs_num_patches(pipeline_key->tcs.tess_input_vertices, nir->info.tess.tcs_vertices_out,
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info->tcs.num_linked_inputs, info->tcs.num_linked_outputs,
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info->tcs.num_linked_patch_outputs,
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device->physical_device->hs.tess_offchip_block_dw_size,
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device->physical_device->rad_info.gfx_level,
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device->physical_device->rad_info.family);
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/* LDS size used by VS+TCS for storing TCS inputs and outputs. */
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info->tcs.num_lds_blocks =
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calculate_tess_lds_size(device->physical_device->rad_info.gfx_level,
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pipeline_key->tcs.tess_input_vertices,
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nir->info.tess.tcs_vertices_out, info->tcs.num_linked_inputs,
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info->num_tess_patches, info->tcs.num_linked_outputs,
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info->tcs.num_linked_patch_outputs);
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break;
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break;
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case MESA_SHADER_VERTEX:
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case MESA_SHADER_VERTEX:
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break;
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break;
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