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radv,aco: use per-attribute vertex descriptors for robustness

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We have to use a different num_records for each attribute to correctly
implement robust buffer access.

fossil-db (GFX10.3, robustBufferAccess enabled):
Totals from 60059 (41.06% of 146267) affected shaders:
VGPRs: 2169040 -> 2169024 (-0.00%); split: -0.02%, +0.02%
CodeSize: 79473128 -> 81156016 (+2.12%); split: -0.00%, +2.12%
MaxWaves: 1635360 -> 1635258 (-0.01%); split: +0.00%, -0.01%
Instrs: 15559040 -> 15793205 (+1.51%); split: -0.01%, +1.52%
Latency: 90954792 -> 91308768 (+0.39%); split: -0.30%, +0.69%
InvThroughput: 14937873 -> 14958761 (+0.14%); split: -0.04%, +0.18%
VClause: 444280 -> 412074 (-7.25%); split: -9.22%, +1.97%
SClause: 588545 -> 644141 (+9.45%); split: -0.54%, +9.99%
Copies: 1010395 -> 1011232 (+0.08%); split: -0.44%, +0.53%
Branches: 274279 -> 274282 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 1431171 -> 1405056 (-1.82%); split: -2.89%, +1.07%
PreVGPRs: 1575253 -> 1575259 (+0.00%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7871>
This commit is contained in:
Rhys Perry
2020-12-01 17:41:16 +00:00
committed by Marge Bot
parent dfa38fa0c7
commit 157c6b0f33
15 changed files with 90 additions and 513 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
src/amd/vulkan/radv_pipeline.c
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@@ -2843,7 +2843,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
if (nir[MESA_SHADER_FRAGMENT]) {
radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT], pipeline->layout,
radv_nir_shader_info_pass(pipeline->device, nir[MESA_SHADER_FRAGMENT], pipeline->layout,
&keys[MESA_SHADER_FRAGMENT], &infos[MESA_SHADER_FRAGMENT]);
/* TODO: These are no longer used as keys we should refactor this */
@@ -2885,7 +2885,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
for (int i = 0; i < 2; i++) {
radv_nir_shader_info_pass(combined_nir[i], pipeline->layout, &key,
radv_nir_shader_info_pass(pipeline->device, combined_nir[i], pipeline->layout, &key,
&infos[MESA_SHADER_TESS_CTRL]);
}
@@ -2902,8 +2902,8 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
for (int i = 0; i < 2; i++) {
radv_nir_shader_info_pass(combined_nir[i], pipeline->layout, &keys[pre_stage],
&infos[MESA_SHADER_GEOMETRY]);
radv_nir_shader_info_pass(pipeline->device, combined_nir[i], pipeline->layout,
&keys[pre_stage], &infos[MESA_SHADER_GEOMETRY]);
}
filled_stages |= (1 << pre_stage);
@@ -2914,7 +2914,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
while (active_stages) {
int i = u_bit_scan(&active_stages);
radv_nir_shader_info_init(&infos[i]);
radv_nir_shader_info_pass(nir[i], pipeline->layout, &keys[i], &infos[i]);
radv_nir_shader_info_pass(pipeline->device, nir[i], pipeline->layout, &keys[i], &infos[i]);
}
for (int i = 0; i < MESA_SHADER_STAGES; i++) {
@@ -3508,7 +3508,8 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_device *device,
key.has_multiview_view_index = keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY], pipeline->layout, &key, &info);
radv_nir_shader_info_pass(device, nir[MESA_SHADER_GEOMETRY], pipeline->layout, &key,
&info);
info.wave_size = 64; /* Wave32 not supported. */
info.ballot_bit_size = 64;
@@ -5303,14 +5304,25 @@ static void
radv_pipeline_init_vertex_input_state(struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
const struct radv_shader_info *info = &radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info;
const VkPipelineVertexInputStateCreateInfo *vi_info = pCreateInfo->pVertexInputState;
for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
const VkVertexInputBindingDescription *desc = &vi_info->pVertexBindingDescriptions[i];
pipeline->binding_stride[desc->binding] = desc->stride;
pipeline->num_vertex_bindings = MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
}
for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
const VkVertexInputAttributeDescription *desc = &vi_info->pVertexAttributeDescriptions[i];
uint32_t end = desc->offset + vk_format_get_blocksize(desc->format);
pipeline->attrib_ends[desc->location] = end;
pipeline->attrib_bindings[desc->location] = desc->binding;
}
pipeline->use_per_attribute_vb_descs = info->vs.use_per_attribute_vb_descs;
pipeline->vb_desc_usage_mask = info->vs.vb_desc_usage_mask;
}
static struct radv_shader_variant *