intel/compiler: Use nir_tex_src_backend1 to pack LOD and array index

Since this lowering is totally Intel specific, we don't have to
introduce the new texture source. We can use the nir_tex_src_backend1
source to pack LOD/LOD Bias and array index into 32 bit single value.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27458>

src/intel/compiler/brw_fs_nir.cpp

@@ -8150,7 +8150,11 @@ fs_nir_emit_texture(nir_to_brw_state &ntb,
          srcs[TEX_LOGICAL_SRC_MCS] = retype(src, BRW_REGISTER_TYPE_D);
          break;
 
-      case nir_tex_src_combined_lod_and_array_index_intel:
+      /* If this parameter is present, we are packing either the explicit LOD
+       * or LOD bias and the array index into a single (32-bit) value when
+       * 32-bit texture coordinates are used.
+       */
+      case nir_tex_src_backend1:
          assert(!got_lod && !got_bias);
          got_lod = true;
 

src/intel/compiler/brw_nir.c

@@ -945,7 +945,6 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
       .lower_offset_filter =
          devinfo->verx10 >= 125 ? lower_xehp_tg4_offset_filter : NULL,
       .lower_invalid_implicit_lod = true,
-      .pack_lod_and_array_index = devinfo->ver >= 20,
    };
 
    /* In the case where TG4 coords are lowered to offsets and we have a