i965/vec4: Implement uclz in the vec4 backend

Commit 28311f9d02 moved ufind_msb lowering to NIR and started emitting
uclz.  Unfortunately, the vec4 backend never actually implemented uclz.

It's trivial to do.  Now it does.

Fixes: 28311f9d02 ("nir: intel/compiler: Move ufind_msb lowering to NIR")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21974>

src/intel/compiler/brw_vec4.h

@@ -214,6 +214,7 @@ public:
    EMIT1(FBH)
    EMIT1(FBL)
    EMIT1(CBIT)
+   EMIT1(LZD)
    EMIT3(MAD)
    EMIT2(ADDC)
    EMIT2(SUBB)

src/intel/compiler/brw_vec4_nir.cpp

@@ -1636,6 +1636,12 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
       break;
    }
 
+   case nir_op_uclz:
+      assert(nir_dest_bit_size(instr->dest.dest) == 32);
+      assert(nir_src_bit_size(instr->src[0].src) == 32);
+      emit(LZD(dst, op[0]));
+      break;
+
    case nir_op_find_lsb:
       assert(nir_dest_bit_size(instr->dest.dest) == 32);
       assert(nir_src_bit_size(instr->src[0].src) == 32);

src/intel/compiler/brw_vec4_visitor.cpp

@@ -183,6 +183,7 @@ ALU3(BFI2)
 ALU1(FBH)
 ALU1(FBL)
 ALU1(CBIT)
+ALU1(LZD)
 ALU3(MAD)
 ALU2_ACC(ADDC)
 ALU2_ACC(SUBB)