From 14f546726e3501cb794c69a3c7c92ca40a78dade Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 8 Feb 2023 20:46:48 -0500 Subject: [PATCH] agx: Lower shared memory offsets to 16-bit Per the hardware requirement. This simplifies instruction selection (it avoids the need to constant fold u2u16 in the backend). Signed-off-by: Alyssa Rosenzweig Part-of: --- src/asahi/compiler/agx_compile.c | 1 + src/asahi/compiler/agx_compiler.h | 1 + .../compiler/agx_nir_lower_shared_bitsize.c | 50 +++++++++++++++++++ src/asahi/compiler/meson.build | 1 + 4 files changed, 53 insertions(+) create mode 100644 src/asahi/compiler/agx_nir_lower_shared_bitsize.c diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c index b889ec30313..e6529488623 100644 --- a/src/asahi/compiler/agx_compile.c +++ b/src/asahi/compiler/agx_compile.c @@ -2248,6 +2248,7 @@ agx_preprocess_nir(nir_shader *nir) NIR_PASS_V(nir, nir_opt_sink, move_all); NIR_PASS_V(nir, nir_opt_move, move_all); NIR_PASS_V(nir, agx_nir_lower_ubo); + NIR_PASS_V(nir, agx_nir_lower_shared_bitsize); NIR_PASS_V(nir, nir_lower_ssbo); } diff --git a/src/asahi/compiler/agx_compiler.h b/src/asahi/compiler/agx_compiler.h index e306aa2c8be..69d9dcc41c6 100644 --- a/src/asahi/compiler/agx_compiler.h +++ b/src/asahi/compiler/agx_compiler.h @@ -830,6 +830,7 @@ bool agx_nir_opt_preamble(nir_shader *s, unsigned *preamble_size); bool agx_nir_lower_load_mask(nir_shader *shader); bool agx_nir_lower_address(nir_shader *shader); bool agx_nir_lower_ubo(nir_shader *shader); +bool agx_nir_lower_shared_bitsize(nir_shader *shader); #ifdef __cplusplus } /* extern C */ diff --git a/src/asahi/compiler/agx_nir_lower_shared_bitsize.c b/src/asahi/compiler/agx_nir_lower_shared_bitsize.c new file mode 100644 index 00000000000..dedd9d67cd8 --- /dev/null +++ b/src/asahi/compiler/agx_nir_lower_shared_bitsize.c @@ -0,0 +1,50 @@ +/* + * Copyright 2022 Alyssa Rosenzweig + * SPDX-License-Identifier: MIT + */ + +#include "compiler/nir/nir_builder.h" +#include "agx_compiler.h" + +/* Local memory instructions require 16-bit offsets, so we add conversions. */ +static bool +pass(struct nir_builder *b, nir_instr *instr, UNUSED void *data) +{ + if (instr->type != nir_instr_type_intrinsic) + return false; + + nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); + switch (intr->intrinsic) { + case nir_intrinsic_load_shared: + case nir_intrinsic_store_shared: + case nir_intrinsic_shared_atomic_add: + case nir_intrinsic_shared_atomic_imin: + case nir_intrinsic_shared_atomic_umin: + case nir_intrinsic_shared_atomic_imax: + case nir_intrinsic_shared_atomic_umax: + case nir_intrinsic_shared_atomic_and: + case nir_intrinsic_shared_atomic_or: + case nir_intrinsic_shared_atomic_xor: + case nir_intrinsic_shared_atomic_exchange: + case nir_intrinsic_shared_atomic_comp_swap: + break; + default: + return false; + } + + nir_src *offset = nir_get_io_offset_src(intr); + if (nir_src_bit_size(*offset) == 16) + return false; + + b->cursor = nir_before_instr(instr); + nir_instr_rewrite_src_ssa(instr, offset, + nir_u2u16(b, nir_ssa_for_src(b, *offset, 1))); + return true; +} + +bool +agx_nir_lower_shared_bitsize(nir_shader *shader) +{ + return nir_shader_instructions_pass( + shader, pass, nir_metadata_block_index | nir_metadata_dominance, NULL); +} diff --git a/src/asahi/compiler/meson.build b/src/asahi/compiler/meson.build index ec5a7aa19c7..61f87ca480e 100644 --- a/src/asahi/compiler/meson.build +++ b/src/asahi/compiler/meson.build @@ -28,6 +28,7 @@ libasahi_agx_files = files( 'agx_nir_lower_zs_emit.c', 'agx_nir_lower_texture.c', 'agx_nir_lower_load_mask.c', + 'agx_nir_lower_shared_bitsize.c', 'agx_nir_lower_ubo.c', 'agx_nir_opt_preamble.c', 'agx_lower_64bit.c',