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intel/fs/xe2+: Update TES payload setup for Xe2 reg size.

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Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
This commit is contained in:
Francisco Jerez
2022-09-07 14:11:05 -07:00
committed by Jordan Justen
parent 4b3243104c
commit 14e1b9ee69
3 changed files with 13 additions and 7 deletions
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2
src/intel/compiler/brw_fs.cpp
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@@ -7145,7 +7145,7 @@ fs_visitor::run_tes()
{
assert(stage == MESA_SHADER_TESS_EVAL);
payload_ = new tes_thread_payload();
payload_ = new tes_thread_payload(*this);
emit_nir_code();

2
src/intel/compiler/brw_fs.h
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@@ -112,7 +112,7 @@ struct tcs_thread_payload : public thread_payload {
};
struct tes_thread_payload : public thread_payload {
tes_thread_payload();
tes_thread_payload(const fs_visitor &v);
fs_reg patch_urb_input;
fs_reg primitive_id;

16
src/intel/compiler/brw_fs_thread_payload.cpp
View File

@@ -77,20 +77,26 @@ tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)
}
}
tes_thread_payload::tes_thread_payload()
tes_thread_payload::tes_thread_payload(const fs_visitor &v)
{
unsigned r = 0;
/* R0: Thread Header. */
patch_urb_input = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD);
primitive_id = brw_vec1_grf(0, 1);
r += reg_unit(v.devinfo);
/* R1-3: gl_TessCoord.xyz. */
for (unsigned i = 0; i < 3; i++)
coords[i] = brw_vec8_grf(1 + i, 0);
for (unsigned i = 0; i < 3; i++) {
coords[i] = brw_vec8_grf(r, 0);
r += reg_unit(v.devinfo);
}
/* R4: URB output handles. */
urb_output = brw_ud8_grf(4, 0);
urb_output = brw_ud8_grf(r, 0);
r += reg_unit(v.devinfo);
num_regs = 5;
num_regs = r;
}
gs_thread_payload::gs_thread_payload(const fs_visitor &v)