OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel/fs: require UNDEFs register offsets to be aligned to REG_SIZE

Browse Source 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18657>
This commit is contained in:
Lionel Landwerlin
2022-09-22 10:14:28 +03:00
committed by Marge Bot
parent 59ecbe3fe2
commit 14b99df7d9
1 changed files with 1 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/intel/compiler/brw_fs_builder.h
View File

@@ -782,6 +782,7 @@ namespace brw {
UNDEF(const dst_reg &dst) const UNDEF(const dst_reg &dst) const
{ {
assert(dst.file == VGRF); assert(dst.file == VGRF);
assert(dst.offset % REG_SIZE == 0);
instruction *inst = emit(SHADER_OPCODE_UNDEF, instruction *inst = emit(SHADER_OPCODE_UNDEF,
retype(dst, BRW_REGISTER_TYPE_UD)); retype(dst, BRW_REGISTER_TYPE_UD));
inst->size_written = shader->alloc.sizes[dst.nr] * REG_SIZE; inst->size_written = shader->alloc.sizes[dst.nr] * REG_SIZE;