diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 4fdece4f5c7..2c980e3f9f5 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -2133,10 +2133,8 @@ isl_surf_supports_ccs(const struct isl_device *dev,
    if (surf->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)
       return false;
 
-   if (isl_format_is_compressed(surf->format))
-      return false;
-
-   if (!isl_is_pow2(isl_format_get_layout(surf->format)->bpb))
+   if (!isl_format_supports_ccs_d(dev->info, surf->format) &&
+       !isl_format_supports_ccs_e(dev->info, surf->format))
       return false;
 
    /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
@@ -2262,15 +2260,6 @@ isl_surf_supports_ccs(const struct isl_device *dev,
           (surf->levels > 1 || surf->logical_level0_px.array_len > 1))
          return false;
 
-      /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
-       * Target(s)", beneath the "Fast Color Clear" bullet (p326):
-       *
-       *     - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
-       *       64bpp, and 128bpp.
-       */
-      if (isl_format_get_layout(surf->format)->bpb < 32)
-         return false;
-
       /* From the Skylake documentation, it is made clear that X-tiling is no
        * longer supported:
        *
diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index 0ad129868aa..9b4359fa24b 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -835,6 +835,12 @@ isl_format_supports_ccs_d(const struct intel_device_info *devinfo,
 
    const struct isl_format_layout *fmtl = isl_format_get_layout(format);
 
+   /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
+    * Target(s)", beneath the "Fast Color Clear" bullet (p326):
+    *
+    *     - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
+    *       64bpp, and 128bpp.
+    */
    return fmtl->bpb == 32 || fmtl->bpb == 64 || fmtl->bpb == 128;
 }