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intel/isl: Unify fmt checks in isl_surf_supports_ccs

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On TGL+, require that the surface format supports CCS_E in order to
support CCS. This aligns with the ISL code that pads the primary
surface for CCS on this platform.

Pre-TGL, require support for either CCS_D or CCS_E.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12398>
This commit is contained in:
Nanley Chery
2021-08-16 08:48:31 -07:00
committed by Marge Bot
parent d9eaabf05d
commit 1433fe7860
2 changed files with 8 additions and 13 deletions
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15
src/intel/isl/isl.c
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@@ -2133,10 +2133,8 @@ isl_surf_supports_ccs(const struct isl_device *dev,
if (surf->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)
return false;
if (isl_format_is_compressed(surf->format))
return false;
if (!isl_is_pow2(isl_format_get_layout(surf->format)->bpb))
if (!isl_format_supports_ccs_d(dev->info, surf->format) &&
!isl_format_supports_ccs_e(dev->info, surf->format))
return false;
/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
@@ -2262,15 +2260,6 @@ isl_surf_supports_ccs(const struct isl_device *dev,
(surf->levels > 1 || surf->logical_level0_px.array_len > 1))
return false;
/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
* Target(s)", beneath the "Fast Color Clear" bullet (p326):
*
* - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
* 64bpp, and 128bpp.
*/
if (isl_format_get_layout(surf->format)->bpb < 32)
return false;
/* From the Skylake documentation, it is made clear that X-tiling is no
* longer supported:
*

6
src/intel/isl/isl_format.c
View File

@@ -835,6 +835,12 @@ isl_format_supports_ccs_d(const struct intel_device_info *devinfo,
const struct isl_format_layout *fmtl = isl_format_get_layout(format);
/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
* Target(s)", beneath the "Fast Color Clear" bullet (p326):
*
* - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
* 64bpp, and 128bpp.
*/
return fmtl->bpb == 32 || fmtl->bpb == 64 || fmtl->bpb == 128;
}