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intel/vec4: Use the new nir_src_is_const and friends

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As of this commit, all uses of const sources either go through a
nir_src_as_<type> helper which handles bit sizes correctly or else are
accompanied by a nir_src_bit_size() == 32 assertion to assert that we
have the size we think we have.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jason Ekstrand
2018-10-20 10:28:51 -05:00
parent 61e15348c4
commit 1413512b4c
3 changed files with 46 additions and 54 deletions
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12
src/intel/compiler/brw_vec4_gs_nir.cpp
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@@ -41,14 +41,14 @@ vec4_gs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
/* The EmitNoIndirectInput flag guarantees our vertex index will
* be constant. We should handle indirects someday.
*/
nir_const_value *vertex = nir_src_as_const_value(instr->src[0]);
nir_const_value *offset_reg = nir_src_as_const_value(instr->src[1]);
const unsigned vertex = nir_src_as_uint(instr->src[0]);
const unsigned offset_reg = nir_src_as_uint(instr->src[1]);
const unsigned input_array_stride = prog_data->urb_read_length * 2;
if (nir_dest_bit_size(instr->dest) == 64) {
src = src_reg(ATTR, input_array_stride * vertex->u32[0] +
instr->const_index[0] + offset_reg->u32[0],
src = src_reg(ATTR, input_array_stride * vertex +
instr->const_index[0] + offset_reg,
glsl_type::dvec4_type);
dst_reg tmp = dst_reg(this, glsl_type::dvec4_type);
@@ -65,8 +65,8 @@ vec4_gs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
/* Make up a type...we have no way of knowing... */
const glsl_type *const type = glsl_type::ivec(instr->num_components);
src = src_reg(ATTR, input_array_stride * vertex->u32[0] +
instr->const_index[0] + offset_reg->u32[0],
src = src_reg(ATTR, input_array_stride * vertex +
instr->const_index[0] + offset_reg,
type);
src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr));