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intel/fs: fixup a64 messages

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And run algebraic when either int64 for float64 are not supported so
those don't end up in the generated code.

Cc: mesa-stable
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17396>
This commit is contained in:
Lionel Landwerlin
2022-07-20 16:53:14 +03:00
committed by Marge Bot
parent 838bbdcf2e
commit 139e8f4635
2 changed files with 2 additions and 2 deletions
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2
src/intel/compiler/brw_fs.cpp
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@@ -6011,7 +6011,7 @@ fs_visitor::optimize()
OPT(split_virtual_grfs);
/* Lower 64 bit MOVs generated by payload lowering. */
if (!devinfo->has_64bit_float && !devinfo->has_64bit_int)
if (!devinfo->has_64bit_float || !devinfo->has_64bit_int)
OPT(opt_algebraic);
OPT(register_coalesce);

2
src/intel/compiler/brw_lower_logical_sends.cpp
View File

@@ -1988,7 +1988,7 @@ emit_a64_oword_block_header(const fs_builder &bld, const fs_reg &addr)
/* We can't do stride 1 with the UNIFORM file, it requires stride 0 */
expanded_addr = ubld.vgrf(BRW_REGISTER_TYPE_UQ);
expanded_addr.stride = 0;
ubld.MOV(expanded_addr, addr);
ubld.MOV(expanded_addr, retype(addr, BRW_REGISTER_TYPE_UQ));
}
fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD);