nir: Allow outputs reads and add the relevant intrinsics.
Normally, we rely on nir_lower_outputs_to_temporaries to create shadow variables for outputs, buffering the results and writing them all out at the end of the program. However, this is infeasible for tessellation control shader outputs. Tessellation control shaders can generate multiple output vertices, and write per-vertex outputs. These are arrays indexed by the vertex number; each thread only writes one element, but can read any other element - including those being concurrently written by other threads. The barrier() intrinsic synchronizes between threads. Even if we tried to shadow every output element (which is of dubious value), we'd have to read updated values in at barrier() time, which means we need to allow output reads. Most stages should continue using nir_lower_outputs_to_temporaries(), but in theory drivers could choose not to if they really wanted. v2: Rebase to accomodate Jason's review feedback. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
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@@ -255,6 +255,8 @@ LOAD(ubo, 1, 1, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
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LOAD(input, 0, 1, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
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LOAD(per_vertex_input, 1, 1, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
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LOAD(ssbo, 1, 1, NIR_INTRINSIC_CAN_ELIMINATE)
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LOAD(output, 0, 1, NIR_INTRINSIC_CAN_ELIMINATE)
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LOAD(per_vertex_output, 1, 1, NIR_INTRINSIC_CAN_ELIMINATE)
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/*
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* Stores work the same way as loads, except now the first register input is
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@@ -161,6 +161,15 @@ load_op(struct lower_io_state *state,
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nir_intrinsic_load_input;
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}
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break;
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case nir_var_shader_out:
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if (per_vertex) {
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op = has_indirect ? nir_intrinsic_load_per_vertex_output_indirect :
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nir_intrinsic_load_per_vertex_output;
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} else {
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op = has_indirect ? nir_intrinsic_load_output_indirect :
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nir_intrinsic_load_output;
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}
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break;
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case nir_var_uniform:
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op = has_indirect ? nir_intrinsic_load_uniform_indirect :
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nir_intrinsic_load_uniform;
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@@ -191,13 +200,16 @@ nir_lower_io_block(nir_block *block, void *void_state)
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if (state->mode != -1 && state->mode != mode)
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continue;
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if (mode != nir_var_shader_in &&
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mode != nir_var_shader_out &&
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mode != nir_var_uniform)
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continue;
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switch (intrin->intrinsic) {
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case nir_intrinsic_load_var: {
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if (mode != nir_var_shader_in && mode != nir_var_uniform)
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continue;
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bool per_vertex =
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is_per_vertex_input(state, intrin->variables[0]->var);
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is_per_vertex_input(state, intrin->variables[0]->var) ||
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is_per_vertex_output(state, intrin->variables[0]->var);
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nir_ssa_def *indirect;
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nir_ssa_def *vertex_index;
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@@ -241,8 +253,7 @@ nir_lower_io_block(nir_block *block, void *void_state)
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}
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case nir_intrinsic_store_var: {
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if (intrin->variables[0]->var->data.mode != nir_var_shader_out)
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continue;
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assert(mode == nir_var_shader_out);
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nir_ssa_def *indirect;
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nir_ssa_def *vertex_index;
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@@ -448,6 +448,8 @@ print_intrinsic_instr(nir_intrinsic_instr *instr, print_state *state)
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case nir_intrinsic_load_per_vertex_input_indirect:
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var_list = &state->shader->inputs;
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break;
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case nir_intrinsic_load_output:
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case nir_intrinsic_load_output_indirect:
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case nir_intrinsic_store_output:
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case nir_intrinsic_store_output_indirect:
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case nir_intrinsic_store_per_vertex_output:
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@@ -405,7 +405,6 @@ validate_intrinsic_instr(nir_intrinsic_instr *instr, validate_state *state)
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(instr->variables[0]->var->data.mode == nir_var_uniform &&
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glsl_get_base_type(type) == GLSL_TYPE_SUBROUTINE));
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assert(instr->num_components == glsl_get_vector_elements(type));
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assert(instr->variables[0]->var->data.mode != nir_var_shader_out);
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break;
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}
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case nir_intrinsic_store_var: {
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@@ -426,7 +425,6 @@ validate_intrinsic_instr(nir_intrinsic_instr *instr, validate_state *state)
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assert(instr->variables[0]->var->data.mode != nir_var_shader_in &&
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instr->variables[0]->var->data.mode != nir_var_uniform &&
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instr->variables[0]->var->data.mode != nir_var_shader_storage);
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assert(instr->variables[1]->var->data.mode != nir_var_shader_out);
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break;
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default:
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break;
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